2 * (c) 2015 Paul Thacker <paul.thacker@microchip.com>
4 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __PIC32_REGS_H__
9 #define __PIC32_REGS_H__
13 /* System Configuration */
14 #define PIC32_CFG_BASE 0x1f800000
16 /* System config register offsets */
22 #define CFGEBIA 0x00c0
23 #define CFGEBIC 0x00d0
25 #define CFGMPLL 0x0100
27 /* Non Volatile Memory (NOR flash) */
28 #define PIC32_NVM_BASE (PIC32_CFG_BASE + 0x0600)
29 /* Oscillator Configuration */
30 #define PIC32_OSC_BASE (PIC32_CFG_BASE + 0x1200)
31 /* Peripheral Pin Select Input */
32 #define PPS_IN_BASE 0x1f801400
33 /* Peripheral Pin Select Output */
34 #define PPS_OUT_BASE 0x1f801500
36 #define PINCTRL_BASE 0x1f860000
39 #define PIC32_USB_CORE_BASE 0x1f8e3000
40 #define PIC32_USB_CTRL_BASE 0x1f884000
43 #define PIC32_SPI1_BASE 0x1f821000
46 #define PREFETCH_BASE 0x1f8e0000
49 #define PIC32_DDR2C_BASE 0x1f8e8000
52 #define PIC32_DDR2P_BASE 0x1f8e9100
55 #define PIC32_EBI_BASE 0x1f8e1000
58 #define PIC32_SQI_BASE 0x1f8e2000
60 struct pic32_reg_atomic {
67 #define _CLR_OFFSET 0x04
68 #define _SET_OFFSET 0x08
69 #define _INV_OFFSET 0x0c
71 static inline void __iomem *pic32_get_syscfg_base(void)
73 return (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE);
76 #endif /* __PIC32_REGS_H__ */