1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (c) 2018 Stefan Roese <sr@denx.de>
5 * This code is mostly based on the code extracted from this MediaTek
8 * https://github.com/MediaTek-Labs/linkit-smart-uboot.git
10 * I was not able to find a specific license or other developers
11 * copyrights here, so I can't add them here.
15 #include <asm/regdef.h>
16 #include <asm/mipsregs.h>
17 #include <asm/addrspace.h>
22 #define BIT(nr) (1 << (nr))
25 #define DELAY_USEC(us) ((us) / 100)
27 #define DDR_CFG1_CHIP_WIDTH_MASK (0x3 << 16)
28 #define DDR_CFG1_BUS_WIDTH_MASK (0x3 << 12)
30 #if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT)
31 #define DDR_CFG1_SIZE_VAL 0x222e2323
32 #define DDR_CFG4_SIZE_VAL 7
34 #if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT)
35 #define DDR_CFG1_SIZE_VAL 0x22322323
36 #define DDR_CFG4_SIZE_VAL 9
38 #if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT)
39 #define DDR_CFG1_SIZE_VAL 0x22362323
40 #define DDR_CFG4_SIZE_VAL 9
42 #if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT)
43 #define DDR_CFG1_SIZE_VAL 0x223a2323
44 #define DDR_CFG4_SIZE_VAL 9
47 #if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_8BIT)
48 #define DDR_CFG1_CHIP_WIDTH_VAL (0x1 << 16)
50 #if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT)
51 #define DDR_CFG1_CHIP_WIDTH_VAL (0x2 << 16)
54 #if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_16BIT)
55 #define DDR_CFG1_BUS_WIDTH_VAL (0x2 << 12)
57 #if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_32BIT)
58 #define DDR_CFG1_BUS_WIDTH_VAL (0x3 << 12)
65 /* Load base addresses as physical addresses for later usage */
66 li s0, CKSEG1ADDR(MT76XX_SYSCTL_BASE)
67 li s1, CKSEG1ADDR(MT76XX_MEMCTRL_BASE)
68 li s2, CKSEG1ADDR(MT76XX_RGCTRL_BASE)
70 /* polling CPLL is ready */
71 li t1, DELAY_USEC(1000000)
72 la t5, MT76XX_ROM_STATUS_REG
80 la t0, MT76XX_CLKCFG0_REG
87 la t0, MT76XX_CLKCFG0_REG
93 la t0, MT76XX_DYN_CFG0_REG
95 li t5, ~((0x0f << 8) | (0x0f << 0))
97 li t5, (10 << 8) | (1 << 0)
100 la t0, MT76XX_CLKCFG0_REG
118 * SDR and DDR initialization: delay 200us
120 li t0, DELAY_USEC(200 + 40)
127 /* set DRAM IO PAD for MT7628IC */
142 /* suppose external DDR1 LDO 2.5V */
152 li t3, DELAY_USEC(250*50)
197 bnez t9, MT7628_AN_DDR1_PAD
211 beqz t1, MT7628_AN_DDR2_PAD
233 li t8, 0x00000000 /* ODT off */
246 * DDR initialization: reset pin to 0
254 * DDR initialization: wait til reg DDR_CFG1 bit 21 equal to 1 (ready)
267 * Only DDR2 supported right now. DDR2 support can be added, once
268 * boards using it will get added to mainline U-Boot.
283 /* Disable ODT; reference board ok, ev board fail */
288 li t2, ~(0x01f | 0x0f0)
290 ori t1, t1, DDR_CFG4_SIZE_VAL
295 * DDR initialization: config size and width on reg DDR_CFG1
297 li t6, DDR_CFG1_SIZE_VAL
299 and t6, ~DDR_CFG1_CHIP_WIDTH_MASK
300 or t6, DDR_CFG1_CHIP_WIDTH_VAL
302 /* CONFIG DDR_CFG1[13:12] about TOTAL WIDTH */
303 and t6, ~DDR_CFG1_BUS_WIDTH_MASK
304 or t6, DDR_CFG1_BUS_WIDTH_VAL
311 * DDR: enable self auto refresh for power saving
312 * enable it by default for both RAM and ROM version (for CoC)