1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Stefan Roese <sr@denx.de>
13 #include <linux/sizes.h>
18 #ifdef CONFIG_BOOT_ROM
19 int mach_cpu_init(void)
29 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_256M);
34 int print_cpuinfo(void)
36 static const char * const boot_str[] = { "PLL (3-Byte SPI Addr)",
37 "PLL (4-Byte SPI Addr)",
38 "XTAL (3-Byte SPI Addr)",
39 "XTAL (4-Byte SPI Addr)" };
40 const void *blob = gd->fdt_blob;
41 void __iomem *sysc_base;
42 char buf[STR_LEN + 1];
49 /* Get system controller base address */
50 node = fdt_node_offset_by_compatible(blob, -1, "ralink,mt7620a-sysc");
52 return -FDT_ERR_NOTFOUND;
54 base = fdtdec_get_addr_size_auto_noparent(blob, node, "reg",
56 if (base == FDT_ADDR_T_NONE)
59 sysc_base = ioremap_nocache(base, size);
61 str = (char *)sysc_base + MT76XX_CHIPID_OFFS;
62 snprintf(buf, STR_LEN + 1, "%s", str);
63 val = readl(sysc_base + MT76XX_CHIP_REV_ID_OFFS);
64 printf("CPU: %-*s Rev %ld.%ld - ", STR_LEN, buf,
65 (val & GENMASK(11, 8)) >> 8, val & GENMASK(3, 0));
67 val = (readl(sysc_base + MT76XX_SYSCFG0_OFFS) & GENMASK(3, 1)) >> 1;
68 printf("Boot from %s\n", boot_str[val]);
73 int last_stage_init(void)
80 printf("Can't allocate buffer for cache cleanup copy!\n");
85 * It has been noticed, that sometimes the d-cache is not in a
86 * "clean-state" when U-Boot is running on MT7688. This was
87 * detected when using the ethernet driver (which uses d-cache)
88 * and a TFTP command does not complete. Copying an area of 64KiB
89 * in DDR at a very late bootup time in U-Boot, directly before
90 * calling into the prompt, seems to fix this issue.
92 memcpy(dst, src, SZ_64K);