1 // SPDX-License-Identifier: GPL-2.0+
3 * Startup Code for MIPS32 XBURST CPU-core
5 * Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
9 #include <asm/regdef.h>
10 #include <asm/mipsregs.h>
11 #include <asm/addrspace.h>
12 #include <asm/cacheops.h>
13 #include <asm/cache.h>
14 #include <mach/jz4780.h>
21 #ifdef CONFIG_SPL_BUILD
23 /* magic value ("MSPL") */
27 mfc0 t0, CP0_CONFIG, 7
30 mtc0 t0, CP0_CONFIG, 7
34 * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
40 /* IV=1, use the specical interrupt vector (0x200) */
44 #ifdef CONFIG_SOC_JZ4780
45 /* enable bridge radical mode */
53 li sp, CONFIG_SPL_STACK
58 #ifdef CONFIG_SOC_JZ4780
67 addu t1, t0, CONFIG_SYS_DCACHE_SIZE
69 cache INDEX_STORE_TAG_D, 0(t0)
71 addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE
74 addu t1, t0, CONFIG_SYS_ICACHE_SIZE
76 cache INDEX_STORE_TAG_I, 0(t0)
78 addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE
81 mfc0 t0, CP0_CONFIG, 7
84 mtc0 t0, CP0_CONFIG, 7
88 li t0, CONF_CM_CACHABLE_NONCOHERENT
97 #endif /* CONFIG_SOC_JZ4780 */
98 #endif /* !CONFIG_SPL_BUILD */