2 * Atheros AR71XX/AR724X/AR913X SoC register definitions
4 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
6 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
9 * SPDX-License-Identifier: GPL-2.0+
12 #ifndef __ASM_MACH_AR71XX_REGS_H
13 #define __ASM_MACH_AR71XX_REGS_H
16 #include <linux/bitops.h>
19 #define BIT(nr) (1 << (nr))
23 #define AR71XX_APB_BASE 0x18000000
24 #define AR71XX_GE0_BASE 0x19000000
25 #define AR71XX_GE0_SIZE 0x10000
26 #define AR71XX_GE1_BASE 0x1a000000
27 #define AR71XX_GE1_SIZE 0x10000
28 #define AR71XX_EHCI_BASE 0x1b000000
29 #define AR71XX_EHCI_SIZE 0x1000
30 #define AR71XX_OHCI_BASE 0x1c000000
31 #define AR71XX_OHCI_SIZE 0x1000
32 #define AR71XX_SPI_BASE 0x1f000000
33 #define AR71XX_SPI_SIZE 0x01000000
35 #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
36 #define AR71XX_DDR_CTRL_SIZE 0x100
37 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
38 #define AR71XX_UART_SIZE 0x100
39 #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
40 #define AR71XX_USB_CTRL_SIZE 0x100
41 #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
42 #define AR71XX_GPIO_SIZE 0x100
43 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
44 #define AR71XX_PLL_SIZE 0x100
45 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
46 #define AR71XX_RESET_SIZE 0x100
47 #define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
48 #define AR71XX_MII_SIZE 0x100
50 #define AR71XX_PCI_MEM_BASE 0x10000000
51 #define AR71XX_PCI_MEM_SIZE 0x07000000
53 #define AR71XX_PCI_WIN0_OFFS 0x10000000
54 #define AR71XX_PCI_WIN1_OFFS 0x11000000
55 #define AR71XX_PCI_WIN2_OFFS 0x12000000
56 #define AR71XX_PCI_WIN3_OFFS 0x13000000
57 #define AR71XX_PCI_WIN4_OFFS 0x14000000
58 #define AR71XX_PCI_WIN5_OFFS 0x15000000
59 #define AR71XX_PCI_WIN6_OFFS 0x16000000
60 #define AR71XX_PCI_WIN7_OFFS 0x07000000
62 #define AR71XX_PCI_CFG_BASE \
63 (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
64 #define AR71XX_PCI_CFG_SIZE 0x100
66 #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
67 #define AR7240_USB_CTRL_SIZE 0x100
68 #define AR7240_OHCI_BASE 0x1b000000
69 #define AR7240_OHCI_SIZE 0x1000
71 #define AR724X_PCI_MEM_BASE 0x10000000
72 #define AR724X_PCI_MEM_SIZE 0x04000000
74 #define AR724X_PCI_CFG_BASE 0x14000000
75 #define AR724X_PCI_CFG_SIZE 0x1000
76 #define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000)
77 #define AR724X_PCI_CRP_SIZE 0x1000
78 #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
79 #define AR724X_PCI_CTRL_SIZE 0x100
81 #define AR724X_EHCI_BASE 0x1b000000
82 #define AR724X_EHCI_SIZE 0x1000
84 #define AR913X_EHCI_BASE 0x1b000000
85 #define AR913X_EHCI_SIZE 0x1000
86 #define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
87 #define AR913X_WMAC_SIZE 0x30000
89 #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
90 #define AR933X_UART_SIZE 0x14
91 #define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
92 #define AR933X_GMAC_SIZE 0x04
93 #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
94 #define AR933X_WMAC_SIZE 0x20000
95 #define AR933X_RTC_BASE (AR71XX_APB_BASE + 0x00107000)
96 #define AR933X_RTC_SIZE 0x1000
97 #define AR933X_EHCI_BASE 0x1b000000
98 #define AR933X_EHCI_SIZE 0x1000
99 #define AR933X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
100 #define AR933X_SRIF_SIZE 0x1000
102 #define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
103 #define AR934X_GMAC_SIZE 0x14
104 #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
105 #define AR934X_WMAC_SIZE 0x20000
106 #define AR934X_EHCI_BASE 0x1b000000
107 #define AR934X_EHCI_SIZE 0x200
108 #define AR934X_NFC_BASE 0x1b000200
109 #define AR934X_NFC_SIZE 0xb8
110 #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
111 #define AR934X_SRIF_SIZE 0x1000
113 #define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
114 #define QCA953X_GMAC_SIZE 0x14
115 #define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
116 #define QCA953X_WMAC_SIZE 0x20000
117 #define QCA953X_RTC_BASE (AR71XX_APB_BASE + 0x00107000)
118 #define QCA953X_RTC_SIZE 0x1000
119 #define QCA953X_EHCI_BASE 0x1b000000
120 #define QCA953X_EHCI_SIZE 0x200
121 #define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
122 #define QCA953X_SRIF_SIZE 0x1000
124 #define QCA953X_PCI_CFG_BASE0 0x14000000
125 #define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
126 #define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
127 #define QCA953X_PCI_MEM_BASE0 0x10000000
128 #define QCA953X_PCI_MEM_SIZE 0x02000000
130 #define QCA955X_PCI_MEM_BASE0 0x10000000
131 #define QCA955X_PCI_MEM_BASE1 0x12000000
132 #define QCA955X_PCI_MEM_SIZE 0x02000000
133 #define QCA955X_PCI_CFG_BASE0 0x14000000
134 #define QCA955X_PCI_CFG_BASE1 0x16000000
135 #define QCA955X_PCI_CFG_SIZE 0x1000
136 #define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
137 #define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
138 #define QCA955X_PCI_CRP_SIZE 0x1000
139 #define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
140 #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
141 #define QCA955X_PCI_CTRL_SIZE 0x100
143 #define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
144 #define QCA955X_GMAC_SIZE 0x40
145 #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
146 #define QCA955X_WMAC_SIZE 0x20000
147 #define QCA955X_EHCI0_BASE 0x1b000000
148 #define QCA955X_EHCI1_BASE 0x1b400000
149 #define QCA955X_EHCI_SIZE 0x1000
150 #define QCA955X_NFC_BASE 0x1b800200
151 #define QCA955X_NFC_SIZE 0xb8
153 #define QCA956X_PCI_MEM_BASE1 0x12000000
154 #define QCA956X_PCI_MEM_SIZE 0x02000000
155 #define QCA956X_PCI_CFG_BASE1 0x16000000
156 #define QCA956X_PCI_CFG_SIZE 0x1000
157 #define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
158 #define QCA956X_PCI_CRP_SIZE 0x1000
159 #define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
160 #define QCA956X_PCI_CTRL_SIZE 0x100
162 #define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
163 #define QCA956X_WMAC_SIZE 0x20000
164 #define QCA956X_EHCI0_BASE 0x1b000000
165 #define QCA956X_EHCI1_BASE 0x1b400000
166 #define QCA956X_EHCI_SIZE 0x200
167 #define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
168 #define QCA956X_GMAC_SIZE 0x64
173 #define AR71XX_DDR_REG_CONFIG 0x00
174 #define AR71XX_DDR_REG_CONFIG2 0x04
175 #define AR71XX_DDR_REG_MODE 0x08
176 #define AR71XX_DDR_REG_EMR 0x0c
177 #define AR71XX_DDR_REG_CONTROL 0x10
178 #define AR71XX_DDR_REG_REFRESH 0x14
179 #define AR71XX_DDR_REG_RD_CYCLE 0x18
180 #define AR71XX_DDR_REG_TAP_CTRL0 0x1c
181 #define AR71XX_DDR_REG_TAP_CTRL1 0x20
183 #define AR71XX_DDR_REG_PCI_WIN0 0x7c
184 #define AR71XX_DDR_REG_PCI_WIN1 0x80
185 #define AR71XX_DDR_REG_PCI_WIN2 0x84
186 #define AR71XX_DDR_REG_PCI_WIN3 0x88
187 #define AR71XX_DDR_REG_PCI_WIN4 0x8c
188 #define AR71XX_DDR_REG_PCI_WIN5 0x90
189 #define AR71XX_DDR_REG_PCI_WIN6 0x94
190 #define AR71XX_DDR_REG_PCI_WIN7 0x98
191 #define AR71XX_DDR_REG_FLUSH_GE0 0x9c
192 #define AR71XX_DDR_REG_FLUSH_GE1 0xa0
193 #define AR71XX_DDR_REG_FLUSH_USB 0xa4
194 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8
196 #define AR724X_DDR_REG_FLUSH_GE0 0x7c
197 #define AR724X_DDR_REG_FLUSH_GE1 0x80
198 #define AR724X_DDR_REG_FLUSH_USB 0x84
199 #define AR724X_DDR_REG_FLUSH_PCIE 0x88
201 #define AR913X_DDR_REG_FLUSH_GE0 0x7c
202 #define AR913X_DDR_REG_FLUSH_GE1 0x80
203 #define AR913X_DDR_REG_FLUSH_USB 0x84
204 #define AR913X_DDR_REG_FLUSH_WMAC 0x88
206 #define AR933X_DDR_REG_FLUSH_GE0 0x7c
207 #define AR933X_DDR_REG_FLUSH_GE1 0x80
208 #define AR933X_DDR_REG_FLUSH_USB 0x84
209 #define AR933X_DDR_REG_FLUSH_WMAC 0x88
210 #define AR933X_DDR_REG_DDR2_CONFIG 0x8c
211 #define AR933X_DDR_REG_EMR2 0x90
212 #define AR933X_DDR_REG_EMR3 0x94
213 #define AR933X_DDR_REG_BURST 0x98
214 #define AR933X_DDR_REG_TIMEOUT_MAX 0x9c
215 #define AR933X_DDR_REG_TIMEOUT_CNT 0x9c
216 #define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c
218 #define AR934X_DDR_REG_FLUSH_GE0 0x9c
219 #define AR934X_DDR_REG_FLUSH_GE1 0xa0
220 #define AR934X_DDR_REG_FLUSH_USB 0xa4
221 #define AR934X_DDR_REG_FLUSH_PCIE 0xa8
222 #define AR934X_DDR_REG_FLUSH_WMAC 0xac
224 #define QCA953X_DDR_REG_FLUSH_GE0 0x9c
225 #define QCA953X_DDR_REG_FLUSH_GE1 0xa0
226 #define QCA953X_DDR_REG_FLUSH_USB 0xa4
227 #define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
228 #define QCA953X_DDR_REG_FLUSH_WMAC 0xac
229 #define QCA953X_DDR_REG_DDR2_CONFIG 0xb8
230 #define QCA953X_DDR_REG_BURST 0xc4
231 #define QCA953X_DDR_REG_BURST2 0xc8
232 #define QCA953X_DDR_REG_TIMEOUT_MAX 0xcc
233 #define QCA953X_DDR_REG_CTL_CONF 0x108
234 #define QCA953X_DDR_REG_CONFIG3 0x15c
239 #define AR71XX_PLL_REG_CPU_CONFIG 0x00
240 #define AR71XX_PLL_REG_SEC_CONFIG 0x04
241 #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
242 #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
244 #define AR71XX_PLL_DIV_SHIFT 3
245 #define AR71XX_PLL_DIV_MASK 0x1f
246 #define AR71XX_CPU_DIV_SHIFT 16
247 #define AR71XX_CPU_DIV_MASK 0x3
248 #define AR71XX_DDR_DIV_SHIFT 18
249 #define AR71XX_DDR_DIV_MASK 0x3
250 #define AR71XX_AHB_DIV_SHIFT 20
251 #define AR71XX_AHB_DIV_MASK 0x7
253 #define AR71XX_ETH0_PLL_SHIFT 17
254 #define AR71XX_ETH1_PLL_SHIFT 19
256 #define AR724X_PLL_REG_CPU_CONFIG 0x00
257 #define AR724X_PLL_REG_PCIE_CONFIG 0x18
259 #define AR724X_PLL_DIV_SHIFT 0
260 #define AR724X_PLL_DIV_MASK 0x3ff
261 #define AR724X_PLL_REF_DIV_SHIFT 10
262 #define AR724X_PLL_REF_DIV_MASK 0xf
263 #define AR724X_AHB_DIV_SHIFT 19
264 #define AR724X_AHB_DIV_MASK 0x1
265 #define AR724X_DDR_DIV_SHIFT 22
266 #define AR724X_DDR_DIV_MASK 0x3
268 #define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
270 #define AR913X_PLL_REG_CPU_CONFIG 0x00
271 #define AR913X_PLL_REG_ETH_CONFIG 0x04
272 #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
273 #define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18
275 #define AR913X_PLL_DIV_SHIFT 0
276 #define AR913X_PLL_DIV_MASK 0x3ff
277 #define AR913X_DDR_DIV_SHIFT 22
278 #define AR913X_DDR_DIV_MASK 0x3
279 #define AR913X_AHB_DIV_SHIFT 19
280 #define AR913X_AHB_DIV_MASK 0x1
282 #define AR913X_ETH0_PLL_SHIFT 20
283 #define AR913X_ETH1_PLL_SHIFT 22
285 #define AR933X_PLL_CPU_CONFIG_REG 0x00
286 #define AR933X_PLL_CLK_CTRL_REG 0x08
287 #define AR933X_PLL_DITHER_FRAC_REG 0x10
289 #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
290 #define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
291 #define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
292 #define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
293 #define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
294 #define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
296 #define AR933X_PLL_CLK_CTRL_BYPASS BIT(2)
297 #define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
298 #define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x3
299 #define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
300 #define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x3
301 #define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
302 #define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x7
304 #define AR934X_PLL_CPU_CONFIG_REG 0x00
305 #define AR934X_PLL_DDR_CONFIG_REG 0x04
306 #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
307 #define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
308 #define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
310 #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
311 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
312 #define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6
313 #define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
314 #define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
315 #define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
316 #define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
317 #define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
319 #define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
320 #define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
321 #define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10
322 #define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
323 #define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
324 #define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
325 #define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
326 #define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
328 #define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
329 #define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
330 #define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
331 #define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
332 #define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
333 #define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
334 #define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
335 #define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
336 #define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
337 #define AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
338 #define AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
339 #define AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
341 #define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL BIT(6)
343 #define QCA953X_PLL_CPU_CONFIG_REG 0x00
344 #define QCA953X_PLL_DDR_CONFIG_REG 0x04
345 #define QCA953X_PLL_CLK_CTRL_REG 0x08
346 #define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
347 #define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
348 #define QCA953X_PLL_DDR_DIT_FRAC_REG 0x44
349 #define QCA953X_PLL_CPU_DIT_FRAC_REG 0x48
351 #define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
352 #define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
353 #define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
354 #define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
355 #define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
356 #define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
357 #define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
358 #define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
360 #define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
361 #define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
362 #define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
363 #define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
364 #define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
365 #define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
366 #define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
367 #define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
369 #define QCA953X_PLL_CONFIG_PWD BIT(30)
371 #define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
372 #define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
373 #define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
374 #define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
375 #define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
376 #define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
377 #define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
378 #define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
379 #define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
380 #define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
381 #define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
382 #define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
384 #define QCA953X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0
385 #define QCA953X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f
386 #define QCA953X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6
387 #define QCA953X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f
388 #define QCA953X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12
389 #define QCA953X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f
390 #define QCA953X_PLL_CPU_DIT_UPD_CNT_SHIFT 18
391 #define QCA953X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f
393 #define QCA953X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0
394 #define QCA953X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff
395 #define QCA953X_PLL_DDR_DIT_FRAC_MIN_SHIFT 9
396 #define QCA953X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff
397 #define QCA953X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20
398 #define QCA953X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f
399 #define QCA953X_PLL_DDR_DIT_UPD_CNT_SHIFT 27
400 #define QCA953X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f
402 #define QCA953X_PLL_DIT_FRAC_EN BIT(31)
404 #define QCA955X_PLL_CPU_CONFIG_REG 0x00
405 #define QCA955X_PLL_DDR_CONFIG_REG 0x04
406 #define QCA955X_PLL_CLK_CTRL_REG 0x08
407 #define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
408 #define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
410 #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
411 #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
412 #define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6
413 #define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f
414 #define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
415 #define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
416 #define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
417 #define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
419 #define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
420 #define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
421 #define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10
422 #define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f
423 #define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
424 #define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
425 #define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
426 #define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
428 #define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
429 #define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
430 #define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
431 #define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
432 #define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
433 #define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
434 #define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
435 #define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
436 #define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
437 #define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
438 #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
439 #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
441 #define QCA956X_PLL_CPU_CONFIG_REG 0x00
442 #define QCA956X_PLL_CPU_CONFIG1_REG 0x04
443 #define QCA956X_PLL_DDR_CONFIG_REG 0x08
444 #define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
445 #define QCA956X_PLL_CLK_CTRL_REG 0x10
447 #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
448 #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
449 #define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
450 #define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
452 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
453 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
454 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
455 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff
456 #define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
457 #define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
459 #define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
460 #define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
461 #define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
462 #define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
464 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
465 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
466 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
467 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff
468 #define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
469 #define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
471 #define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
472 #define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
473 #define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
474 #define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
475 #define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
476 #define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
477 #define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
478 #define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
479 #define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
480 #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20)
481 #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
482 #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
487 #define AR71XX_USB_CTRL_REG_FLADJ 0x00
488 #define AR71XX_USB_CTRL_REG_CONFIG 0x04
493 #define AR71XX_RESET_REG_TIMER 0x00
494 #define AR71XX_RESET_REG_TIMER_RELOAD 0x04
495 #define AR71XX_RESET_REG_WDOG_CTRL 0x08
496 #define AR71XX_RESET_REG_WDOG 0x0c
497 #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
498 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
499 #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
500 #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
501 #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
502 #define AR71XX_RESET_REG_RESET_MODULE 0x24
503 #define AR71XX_RESET_REG_PERFC_CTRL 0x2c
504 #define AR71XX_RESET_REG_PERFC0 0x30
505 #define AR71XX_RESET_REG_PERFC1 0x34
506 #define AR71XX_RESET_REG_REV_ID 0x90
508 #define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18
509 #define AR913X_RESET_REG_RESET_MODULE 0x1c
510 #define AR913X_RESET_REG_PERF_CTRL 0x20
511 #define AR913X_RESET_REG_PERFC0 0x24
512 #define AR913X_RESET_REG_PERFC1 0x28
514 #define AR724X_RESET_REG_RESET_MODULE 0x1c
516 #define AR933X_RESET_REG_RESET_MODULE 0x1c
517 #define AR933X_RESET_REG_BOOTSTRAP 0xac
519 #define AR934X_RESET_REG_RESET_MODULE 0x1c
520 #define AR934X_RESET_REG_BOOTSTRAP 0xb0
521 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
523 #define QCA953X_RESET_REG_RESET_MODULE 0x1c
524 #define QCA953X_RESET_REG_BOOTSTRAP 0xb0
525 #define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
527 #define QCA955X_RESET_REG_RESET_MODULE 0x1c
528 #define QCA955X_RESET_REG_BOOTSTRAP 0xb0
529 #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
531 #define QCA956X_RESET_REG_RESET_MODULE 0x1c
532 #define QCA956X_RESET_REG_BOOTSTRAP 0xb0
533 #define QCA956X_RESET_REG_EXT_INT_STATUS 0xac
535 #define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28)
536 #define MISC_INT_ETHSW BIT(12)
537 #define MISC_INT_TIMER4 BIT(10)
538 #define MISC_INT_TIMER3 BIT(9)
539 #define MISC_INT_TIMER2 BIT(8)
540 #define MISC_INT_DMA BIT(7)
541 #define MISC_INT_OHCI BIT(6)
542 #define MISC_INT_PERFC BIT(5)
543 #define MISC_INT_WDOG BIT(4)
544 #define MISC_INT_UART BIT(3)
545 #define MISC_INT_GPIO BIT(2)
546 #define MISC_INT_ERROR BIT(1)
547 #define MISC_INT_TIMER BIT(0)
549 #define AR71XX_RESET_EXTERNAL BIT(28)
550 #define AR71XX_RESET_FULL_CHIP BIT(24)
551 #define AR71XX_RESET_CPU_NMI BIT(21)
552 #define AR71XX_RESET_CPU_COLD BIT(20)
553 #define AR71XX_RESET_DMA BIT(19)
554 #define AR71XX_RESET_SLIC BIT(18)
555 #define AR71XX_RESET_STEREO BIT(17)
556 #define AR71XX_RESET_DDR BIT(16)
557 #define AR71XX_RESET_GE1_MAC BIT(13)
558 #define AR71XX_RESET_GE1_PHY BIT(12)
559 #define AR71XX_RESET_USBSUS_OVERRIDE BIT(10)
560 #define AR71XX_RESET_GE0_MAC BIT(9)
561 #define AR71XX_RESET_GE0_PHY BIT(8)
562 #define AR71XX_RESET_USB_OHCI_DLL BIT(6)
563 #define AR71XX_RESET_USB_HOST BIT(5)
564 #define AR71XX_RESET_USB_PHY BIT(4)
565 #define AR71XX_RESET_PCI_BUS BIT(1)
566 #define AR71XX_RESET_PCI_CORE BIT(0)
568 #define AR7240_RESET_USB_HOST BIT(5)
569 #define AR7240_RESET_OHCI_DLL BIT(3)
571 #define AR724X_RESET_GE1_MDIO BIT(23)
572 #define AR724X_RESET_GE0_MDIO BIT(22)
573 #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
574 #define AR724X_RESET_PCIE_PHY BIT(7)
575 #define AR724X_RESET_PCIE BIT(6)
576 #define AR724X_RESET_USB_HOST BIT(5)
577 #define AR724X_RESET_USB_PHY BIT(4)
578 #define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
580 #define AR913X_RESET_AMBA2WMAC BIT(22)
581 #define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
582 #define AR913X_RESET_USB_HOST BIT(5)
583 #define AR913X_RESET_USB_PHY BIT(4)
585 #define AR933X_RESET_GE1_MDIO BIT(23)
586 #define AR933X_RESET_GE0_MDIO BIT(22)
587 #define AR933X_RESET_GE1_MAC BIT(13)
588 #define AR933X_RESET_WMAC BIT(11)
589 #define AR933X_RESET_GE0_MAC BIT(9)
590 #define AR933X_RESET_USB_HOST BIT(5)
591 #define AR933X_RESET_USB_PHY BIT(4)
592 #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
594 #define AR934X_RESET_HOST BIT(31)
595 #define AR934X_RESET_SLIC BIT(30)
596 #define AR934X_RESET_HDMA BIT(29)
597 #define AR934X_RESET_EXTERNAL BIT(28)
598 #define AR934X_RESET_RTC BIT(27)
599 #define AR934X_RESET_PCIE_EP_INT BIT(26)
600 #define AR934X_RESET_CHKSUM_ACC BIT(25)
601 #define AR934X_RESET_FULL_CHIP BIT(24)
602 #define AR934X_RESET_GE1_MDIO BIT(23)
603 #define AR934X_RESET_GE0_MDIO BIT(22)
604 #define AR934X_RESET_CPU_NMI BIT(21)
605 #define AR934X_RESET_CPU_COLD BIT(20)
606 #define AR934X_RESET_HOST_RESET_INT BIT(19)
607 #define AR934X_RESET_PCIE_EP BIT(18)
608 #define AR934X_RESET_UART1 BIT(17)
609 #define AR934X_RESET_DDR BIT(16)
610 #define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
611 #define AR934X_RESET_NANDF BIT(14)
612 #define AR934X_RESET_GE1_MAC BIT(13)
613 #define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
614 #define AR934X_RESET_USB_PHY_ANALOG BIT(11)
615 #define AR934X_RESET_HOST_DMA_INT BIT(10)
616 #define AR934X_RESET_GE0_MAC BIT(9)
617 #define AR934X_RESET_ETH_SWITCH BIT(8)
618 #define AR934X_RESET_PCIE_PHY BIT(7)
619 #define AR934X_RESET_PCIE BIT(6)
620 #define AR934X_RESET_USB_HOST BIT(5)
621 #define AR934X_RESET_USB_PHY BIT(4)
622 #define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
623 #define AR934X_RESET_LUT BIT(2)
624 #define AR934X_RESET_MBOX BIT(1)
625 #define AR934X_RESET_I2S BIT(0)
627 #define QCA953X_RESET_USB_EXT_PWR BIT(29)
628 #define QCA953X_RESET_EXTERNAL BIT(28)
629 #define QCA953X_RESET_RTC BIT(27)
630 #define QCA953X_RESET_FULL_CHIP BIT(24)
631 #define QCA953X_RESET_GE1_MDIO BIT(23)
632 #define QCA953X_RESET_GE0_MDIO BIT(22)
633 #define QCA953X_RESET_CPU_NMI BIT(21)
634 #define QCA953X_RESET_CPU_COLD BIT(20)
635 #define QCA953X_RESET_DDR BIT(16)
636 #define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
637 #define QCA953X_RESET_GE1_MAC BIT(13)
638 #define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12)
639 #define QCA953X_RESET_USB_PHY_ANALOG BIT(11)
640 #define QCA953X_RESET_GE0_MAC BIT(9)
641 #define QCA953X_RESET_ETH_SWITCH BIT(8)
642 #define QCA953X_RESET_PCIE_PHY BIT(7)
643 #define QCA953X_RESET_PCIE BIT(6)
644 #define QCA953X_RESET_USB_HOST BIT(5)
645 #define QCA953X_RESET_USB_PHY BIT(4)
646 #define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
648 #define QCA955X_RESET_HOST BIT(31)
649 #define QCA955X_RESET_SLIC BIT(30)
650 #define QCA955X_RESET_HDMA BIT(29)
651 #define QCA955X_RESET_EXTERNAL BIT(28)
652 #define QCA955X_RESET_RTC BIT(27)
653 #define QCA955X_RESET_PCIE_EP_INT BIT(26)
654 #define QCA955X_RESET_CHKSUM_ACC BIT(25)
655 #define QCA955X_RESET_FULL_CHIP BIT(24)
656 #define QCA955X_RESET_GE1_MDIO BIT(23)
657 #define QCA955X_RESET_GE0_MDIO BIT(22)
658 #define QCA955X_RESET_CPU_NMI BIT(21)
659 #define QCA955X_RESET_CPU_COLD BIT(20)
660 #define QCA955X_RESET_HOST_RESET_INT BIT(19)
661 #define QCA955X_RESET_PCIE_EP BIT(18)
662 #define QCA955X_RESET_UART1 BIT(17)
663 #define QCA955X_RESET_DDR BIT(16)
664 #define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
665 #define QCA955X_RESET_NANDF BIT(14)
666 #define QCA955X_RESET_GE1_MAC BIT(13)
667 #define QCA955X_RESET_SGMII_ANALOG BIT(12)
668 #define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
669 #define QCA955X_RESET_HOST_DMA_INT BIT(10)
670 #define QCA955X_RESET_GE0_MAC BIT(9)
671 #define QCA955X_RESET_SGMII BIT(8)
672 #define QCA955X_RESET_PCIE_PHY BIT(7)
673 #define QCA955X_RESET_PCIE BIT(6)
674 #define QCA955X_RESET_USB_HOST BIT(5)
675 #define QCA955X_RESET_USB_PHY BIT(4)
676 #define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
677 #define QCA955X_RESET_LUT BIT(2)
678 #define QCA955X_RESET_MBOX BIT(1)
679 #define QCA955X_RESET_I2S BIT(0)
681 #define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
682 #define AR933X_BOOTSTRAP_DDR2 BIT(13)
683 #define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
684 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
686 #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
687 #define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
688 #define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
689 #define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
690 #define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
691 #define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
692 #define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
693 #define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
694 #define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
695 #define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
696 #define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
697 #define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
698 #define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
699 #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
700 #define AR934X_BOOTSTRAP_DDR1 BIT(0)
702 #define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
703 #define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
704 #define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
705 #define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
706 #define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
707 #define QCA953X_BOOTSTRAP_DDR1 BIT(0)
709 #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
711 #define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2)
713 #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
714 #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
715 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
716 #define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
717 #define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
718 #define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
719 #define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
720 #define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
721 #define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
722 #define AR934X_PCIE_WMAC_INT_WMAC_ALL \
723 (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
724 AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
726 #define AR934X_PCIE_WMAC_INT_PCIE_ALL \
727 (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
728 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
729 AR934X_PCIE_WMAC_INT_PCIE_RC3)
731 #define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
732 #define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1)
733 #define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
734 #define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
735 #define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4)
736 #define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
737 #define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
738 #define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
739 #define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
740 #define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
741 (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
742 QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
744 #define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
745 (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
746 QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
747 QCA953X_PCIE_WMAC_INT_PCIE_RC3)
749 #define QCA955X_EXT_INT_WMAC_MISC BIT(0)
750 #define QCA955X_EXT_INT_WMAC_TX BIT(1)
751 #define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
752 #define QCA955X_EXT_INT_WMAC_RXHP BIT(3)
753 #define QCA955X_EXT_INT_PCIE_RC1 BIT(4)
754 #define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5)
755 #define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6)
756 #define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7)
757 #define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8)
758 #define QCA955X_EXT_INT_PCIE_RC2 BIT(12)
759 #define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13)
760 #define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14)
761 #define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15)
762 #define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16)
763 #define QCA955X_EXT_INT_USB1 BIT(24)
764 #define QCA955X_EXT_INT_USB2 BIT(28)
766 #define QCA955X_EXT_INT_WMAC_ALL \
767 (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
768 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
770 #define QCA955X_EXT_INT_PCIE_RC1_ALL \
771 (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
772 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
773 QCA955X_EXT_INT_PCIE_RC1_INT3)
775 #define QCA955X_EXT_INT_PCIE_RC2_ALL \
776 (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
777 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
778 QCA955X_EXT_INT_PCIE_RC2_INT3)
780 #define QCA956X_EXT_INT_WMAC_MISC BIT(0)
781 #define QCA956X_EXT_INT_WMAC_TX BIT(1)
782 #define QCA956X_EXT_INT_WMAC_RXLP BIT(2)
783 #define QCA956X_EXT_INT_WMAC_RXHP BIT(3)
784 #define QCA956X_EXT_INT_PCIE_RC1 BIT(4)
785 #define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5)
786 #define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6)
787 #define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7)
788 #define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8)
789 #define QCA956X_EXT_INT_PCIE_RC2 BIT(12)
790 #define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13)
791 #define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14)
792 #define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15)
793 #define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16)
794 #define QCA956X_EXT_INT_USB1 BIT(24)
795 #define QCA956X_EXT_INT_USB2 BIT(28)
797 #define QCA956X_EXT_INT_WMAC_ALL \
798 (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
799 QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
801 #define QCA956X_EXT_INT_PCIE_RC1_ALL \
802 (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
803 QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
804 QCA956X_EXT_INT_PCIE_RC1_INT3)
806 #define QCA956X_EXT_INT_PCIE_RC2_ALL \
807 (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
808 QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
809 QCA956X_EXT_INT_PCIE_RC2_INT3)
811 #define REV_ID_MAJOR_MASK 0xfff0
812 #define REV_ID_MAJOR_AR71XX 0x00a0
813 #define REV_ID_MAJOR_AR913X 0x00b0
814 #define REV_ID_MAJOR_AR7240 0x00c0
815 #define REV_ID_MAJOR_AR7241 0x0100
816 #define REV_ID_MAJOR_AR7242 0x1100
817 #define REV_ID_MAJOR_AR9330 0x0110
818 #define REV_ID_MAJOR_AR9331 0x1110
819 #define REV_ID_MAJOR_AR9341 0x0120
820 #define REV_ID_MAJOR_AR9342 0x1120
821 #define REV_ID_MAJOR_AR9344 0x2120
822 #define REV_ID_MAJOR_QCA9533 0x0140
823 #define REV_ID_MAJOR_QCA9533_V2 0x0160
824 #define REV_ID_MAJOR_QCA9556 0x0130
825 #define REV_ID_MAJOR_QCA9558 0x1130
826 #define REV_ID_MAJOR_TP9343 0x0150
827 #define REV_ID_MAJOR_QCA9561 0x1150
829 #define AR71XX_REV_ID_MINOR_MASK 0x3
830 #define AR71XX_REV_ID_MINOR_AR7130 0x0
831 #define AR71XX_REV_ID_MINOR_AR7141 0x1
832 #define AR71XX_REV_ID_MINOR_AR7161 0x2
833 #define AR913X_REV_ID_MINOR_AR9130 0x0
834 #define AR913X_REV_ID_MINOR_AR9132 0x1
836 #define AR71XX_REV_ID_REVISION_MASK 0x3
837 #define AR71XX_REV_ID_REVISION_SHIFT 2
838 #define AR71XX_REV_ID_REVISION2_MASK 0xf
843 #define AR933X_RTC_REG_RESET 0x40
844 #define AR933X_RTC_REG_STATUS 0x44
845 #define AR933X_RTC_REG_DERIVED 0x48
846 #define AR933X_RTC_REG_FORCE_WAKE 0x4c
847 #define AR933X_RTC_REG_INT_CAUSE 0x50
848 #define AR933X_RTC_REG_CAUSE_CLR 0x50
849 #define AR933X_RTC_REG_INT_ENABLE 0x54
850 #define AR933X_RTC_REG_INT_MASKE 0x58
852 #define QCA953X_RTC_REG_SYNC_RESET 0x40
853 #define QCA953X_RTC_REG_SYNC_STATUS 0x44
858 #define AR71XX_SPI_REG_FS 0x00
859 #define AR71XX_SPI_REG_CTRL 0x04
860 #define AR71XX_SPI_REG_IOC 0x08
861 #define AR71XX_SPI_REG_RDS 0x0c
863 #define AR71XX_SPI_FS_GPIO BIT(0)
865 #define AR71XX_SPI_CTRL_RD BIT(6)
866 #define AR71XX_SPI_CTRL_DIV_MASK 0x3f
868 #define AR71XX_SPI_IOC_DO BIT(0)
869 #define AR71XX_SPI_IOC_CLK BIT(8)
870 #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
871 #define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0)
872 #define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1)
873 #define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2)
874 #define AR71XX_SPI_IOC_CS_ALL \
875 (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | AR71XX_SPI_IOC_CS2)
880 #define AR71XX_GPIO_REG_OE 0x00
881 #define AR71XX_GPIO_REG_IN 0x04
882 #define AR71XX_GPIO_REG_OUT 0x08
883 #define AR71XX_GPIO_REG_SET 0x0c
884 #define AR71XX_GPIO_REG_CLEAR 0x10
885 #define AR71XX_GPIO_REG_INT_MODE 0x14
886 #define AR71XX_GPIO_REG_INT_TYPE 0x18
887 #define AR71XX_GPIO_REG_INT_POLARITY 0x1c
888 #define AR71XX_GPIO_REG_INT_PENDING 0x20
889 #define AR71XX_GPIO_REG_INT_ENABLE 0x24
890 #define AR71XX_GPIO_REG_FUNC 0x28
891 #define AR933X_GPIO_REG_FUNC 0x30
893 #define AR934X_GPIO_REG_OUT_FUNC0 0x2c
894 #define AR934X_GPIO_REG_OUT_FUNC1 0x30
895 #define AR934X_GPIO_REG_OUT_FUNC2 0x34
896 #define AR934X_GPIO_REG_OUT_FUNC3 0x38
897 #define AR934X_GPIO_REG_OUT_FUNC4 0x3c
898 #define AR934X_GPIO_REG_OUT_FUNC5 0x40
899 #define AR934X_GPIO_REG_FUNC 0x6c
901 #define QCA953X_GPIO_REG_OUT_FUNC0 0x2c
902 #define QCA953X_GPIO_REG_OUT_FUNC1 0x30
903 #define QCA953X_GPIO_REG_OUT_FUNC2 0x34
904 #define QCA953X_GPIO_REG_OUT_FUNC3 0x38
905 #define QCA953X_GPIO_REG_OUT_FUNC4 0x3c
906 #define QCA953X_GPIO_REG_IN_ENABLE0 0x44
907 #define QCA953X_GPIO_REG_FUNC 0x6c
909 #define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
910 #define QCA955X_GPIO_REG_OUT_FUNC1 0x30
911 #define QCA955X_GPIO_REG_OUT_FUNC2 0x34
912 #define QCA955X_GPIO_REG_OUT_FUNC3 0x38
913 #define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
914 #define QCA955X_GPIO_REG_OUT_FUNC5 0x40
915 #define QCA955X_GPIO_REG_FUNC 0x6c
917 #define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
918 #define QCA956X_GPIO_REG_OUT_FUNC1 0x30
919 #define QCA956X_GPIO_REG_OUT_FUNC2 0x34
920 #define QCA956X_GPIO_REG_OUT_FUNC3 0x38
921 #define QCA956X_GPIO_REG_OUT_FUNC4 0x3c
922 #define QCA956X_GPIO_REG_OUT_FUNC5 0x40
923 #define QCA956X_GPIO_REG_IN_ENABLE0 0x44
924 #define QCA956X_GPIO_REG_IN_ENABLE3 0x50
925 #define QCA956X_GPIO_REG_FUNC 0x6c
927 #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
928 #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
929 #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
930 #define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
931 #define AR71XX_GPIO_FUNC_UART_EN BIT(8)
932 #define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
933 #define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
935 #define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
936 #define AR724X_GPIO_FUNC_SPI_EN BIT(18)
937 #define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
938 #define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
939 #define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
940 #define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
941 #define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
942 #define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
943 #define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
944 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
945 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
946 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
947 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
948 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
949 #define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
950 #define AR724X_GPIO_FUNC_UART_EN BIT(1)
951 #define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
953 #define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
954 #define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
955 #define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
956 #define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
957 #define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
958 #define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
959 #define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
960 #define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
961 #define AR913X_GPIO_FUNC_UART_EN BIT(8)
962 #define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
964 #define AR933X_GPIO(x) BIT(x)
965 #define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
966 #define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
967 #define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
968 #define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
969 #define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
970 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
971 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
972 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
973 #define AR933X_GPIO_FUNC_SPI_EN BIT(18)
974 #define AR933X_GPIO_FUNC_RES_TRUE BIT(15)
975 #define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
976 #define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
977 #define AR933X_GPIO_FUNC_XLNA_EN BIT(12)
978 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
979 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
980 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
981 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
982 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
983 #define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
984 #define AR933X_GPIO_FUNC_UART_EN BIT(1)
985 #define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
987 #define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
988 #define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
989 #define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
990 #define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
991 #define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
992 #define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
993 #define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
994 #define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2)
995 #define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1)
997 #define AR934X_GPIO_OUT_GPIO 0
998 #define AR934X_GPIO_OUT_SPI_CS1 7
999 #define AR934X_GPIO_OUT_LED_LINK0 41
1000 #define AR934X_GPIO_OUT_LED_LINK1 42
1001 #define AR934X_GPIO_OUT_LED_LINK2 43
1002 #define AR934X_GPIO_OUT_LED_LINK3 44
1003 #define AR934X_GPIO_OUT_LED_LINK4 45
1004 #define AR934X_GPIO_OUT_EXT_LNA0 46
1005 #define AR934X_GPIO_OUT_EXT_LNA1 47
1007 #define QCA953X_GPIO(x) BIT(x)
1008 #define QCA953X_GPIO_MUX_MASK(x) (0xff << (x))
1009 #define QCA953X_GPIO_OUT_MUX_SPI_CS1 10
1010 #define QCA953X_GPIO_OUT_MUX_SPI_CS2 11
1011 #define QCA953X_GPIO_OUT_MUX_SPI_CS0 9
1012 #define QCA953X_GPIO_OUT_MUX_SPI_CLK 8
1013 #define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12
1014 #define QCA953X_GPIO_OUT_MUX_UART0_SOUT 22
1015 #define QCA953X_GPIO_OUT_MUX_LED_LINK1 41
1016 #define QCA953X_GPIO_OUT_MUX_LED_LINK2 42
1017 #define QCA953X_GPIO_OUT_MUX_LED_LINK3 43
1018 #define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
1019 #define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
1021 #define QCA953X_GPIO_IN_MUX_UART0_SIN 9
1022 #define QCA953X_GPIO_IN_MUX_SPI_DATA_IN 8
1024 #define QCA956X_GPIO_OUT_MUX_GE0_MDO 32
1025 #define QCA956X_GPIO_OUT_MUX_GE0_MDC 33
1027 #define AR71XX_GPIO_COUNT 16
1028 #define AR7240_GPIO_COUNT 18
1029 #define AR7241_GPIO_COUNT 20
1030 #define AR913X_GPIO_COUNT 22
1031 #define AR933X_GPIO_COUNT 30
1032 #define AR934X_GPIO_COUNT 23
1033 #define QCA953X_GPIO_COUNT 18
1034 #define QCA955X_GPIO_COUNT 24
1035 #define QCA956X_GPIO_COUNT 23
1040 #define AR933X_SRIF_DDR_DPLL1_REG 0x240
1041 #define AR933X_SRIF_DDR_DPLL2_REG 0x244
1042 #define AR933X_SRIF_DDR_DPLL3_REG 0x248
1043 #define AR933X_SRIF_DDR_DPLL4_REG 0x24c
1045 #define AR934X_SRIF_CPU_DPLL1_REG 0x1c0
1046 #define AR934X_SRIF_CPU_DPLL2_REG 0x1c4
1047 #define AR934X_SRIF_CPU_DPLL3_REG 0x1c8
1049 #define AR934X_SRIF_DDR_DPLL1_REG 0x240
1050 #define AR934X_SRIF_DDR_DPLL2_REG 0x244
1051 #define AR934X_SRIF_DDR_DPLL3_REG 0x248
1053 #define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27
1054 #define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f
1055 #define AR934X_SRIF_DPLL1_NINT_SHIFT 18
1056 #define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff
1057 #define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
1059 #define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30)
1060 #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
1061 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
1063 #define QCA953X_SRIF_BB_DPLL1_REG 0x180
1064 #define QCA953X_SRIF_BB_DPLL2_REG 0x184
1065 #define QCA953X_SRIF_BB_DPLL3_REG 0x188
1067 #define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0
1068 #define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4
1069 #define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8
1071 #define QCA953X_SRIF_DDR_DPLL1_REG 0x240
1072 #define QCA953X_SRIF_DDR_DPLL2_REG 0x244
1073 #define QCA953X_SRIF_DDR_DPLL3_REG 0x248
1075 #define QCA953X_SRIF_PCIE_DPLL1_REG 0xc00
1076 #define QCA953X_SRIF_PCIE_DPLL2_REG 0xc04
1077 #define QCA953X_SRIF_PCIE_DPLL3_REG 0xc08
1079 #define QCA953X_SRIF_PMU1_REG 0xc40
1080 #define QCA953X_SRIF_PMU2_REG 0xc44
1082 #define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27
1083 #define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
1085 #define QCA953X_SRIF_DPLL1_NINT_SHIFT 18
1086 #define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff
1087 #define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
1089 #define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30)
1091 #define QCA953X_SRIF_DPLL2_KI_SHIFT 29
1092 #define QCA953X_SRIF_DPLL2_KI_MASK 0x3
1094 #define QCA953X_SRIF_DPLL2_KD_SHIFT 25
1095 #define QCA953X_SRIF_DPLL2_KD_MASK 0xf
1097 #define QCA953X_SRIF_DPLL2_PWD BIT(22)
1099 #define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13
1100 #define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
1105 #define AR71XX_MII_REG_MII0_CTRL 0x00
1106 #define AR71XX_MII_REG_MII1_CTRL 0x04
1108 #define AR71XX_MII_CTRL_IF_MASK 3
1109 #define AR71XX_MII_CTRL_SPEED_SHIFT 4
1110 #define AR71XX_MII_CTRL_SPEED_MASK 3
1111 #define AR71XX_MII_CTRL_SPEED_10 0
1112 #define AR71XX_MII_CTRL_SPEED_100 1
1113 #define AR71XX_MII_CTRL_SPEED_1000 2
1115 #define AR71XX_MII0_CTRL_IF_GMII 0
1116 #define AR71XX_MII0_CTRL_IF_MII 1
1117 #define AR71XX_MII0_CTRL_IF_RGMII 2
1118 #define AR71XX_MII0_CTRL_IF_RMII 3
1120 #define AR71XX_MII1_CTRL_IF_RGMII 0
1121 #define AR71XX_MII1_CTRL_IF_RMII 1
1124 * AR933X GMAC interface
1126 #define AR933X_GMAC_REG_ETH_CFG 0x00
1128 #define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
1129 #define AR933X_ETH_CFG_MII_GE0 BIT(1)
1130 #define AR933X_ETH_CFG_GMII_GE0 BIT(2)
1131 #define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
1132 #define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
1133 #define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
1134 #define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
1135 #define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
1136 #define AR933X_ETH_CFG_RMII_GE0 BIT(9)
1137 #define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
1138 #define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
1141 * AR934X GMAC Interface
1143 #define AR934X_GMAC_REG_ETH_CFG 0x00
1145 #define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
1146 #define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
1147 #define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
1148 #define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
1149 #define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
1150 #define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
1151 #define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
1152 #define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
1153 #define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
1154 #define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
1155 #define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
1156 #define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
1157 #define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
1158 #define AR934X_ETH_CFG_RXD_DELAY BIT(14)
1159 #define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3
1160 #define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14
1161 #define AR934X_ETH_CFG_RDV_DELAY BIT(16)
1162 #define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
1163 #define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
1166 * QCA953X GMAC Interface
1168 #define QCA953X_GMAC_REG_ETH_CFG 0x00
1170 #define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6)
1171 #define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7)
1172 #define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9)
1173 #define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
1176 * QCA955X GMAC Interface
1179 #define QCA955X_GMAC_REG_ETH_CFG 0x00
1181 #define QCA955X_ETH_CFG_RGMII_EN BIT(0)
1182 #define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
1184 #endif /* __ASM_AR71XX_H */