1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
7 #include <clock_legacy.h>
9 #include <asm/addrspace.h>
10 #include <asm/types.h>
11 #include <mach/ar71xx_regs.h>
12 #include <mach/ath79.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 static u32 ar933x_get_xtal(void)
20 val = ath79_get_bootstrap();
21 if (val & AR933X_BOOTSTRAP_REF_CLK_40)
27 int get_serial_clock(void)
29 return ar933x_get_xtal();
35 u32 val, xtal, pll, div;
37 regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
39 xtal = ar933x_get_xtal();
40 val = readl(regs + AR933X_PLL_CPU_CONFIG_REG);
42 /* VCOOUT = XTAL * DIV_INT */
43 div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT)
44 & AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
47 /* PLLOUT = VCOOUT * (1/2^OUTDIV) */
48 div = (val >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT)
49 & AR933X_PLL_CPU_CONFIG_NINT_MASK;
51 div = (val >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
52 & AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
57 val = readl(regs + AR933X_PLL_CLK_CTRL_REG);
59 /* CPU_CLK = PLLOUT / CPU_POST_DIV */
60 div = ((val >> AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
61 & AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
62 gd->cpu_clk = pll / div;
64 /* DDR_CLK = PLLOUT / DDR_POST_DIV */
65 div = ((val >> AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
66 & AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
67 gd->mem_clk = pll / div;
69 /* AHB_CLK = PLLOUT / AHB_POST_DIV */
70 div = ((val >> AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
71 & AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1;
72 gd->bus_clk = pll / div;
77 ulong get_bus_freq(ulong dummy)
84 ulong get_ddr_freq(ulong dummy)