2 * Cache-handling routined for MIPS CPUs
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm-offsets.h>
12 #include <asm/regdef.h>
13 #include <asm/mipsregs.h>
14 #include <asm/addrspace.h>
15 #include <asm/cacheops.h>
17 #ifndef CONFIG_SYS_MIPS_CACHE_MODE
18 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
21 #define INDEX_BASE CKSEG0
23 .macro f_fill64 dst, offset, val
24 LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
25 LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
26 LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
27 LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
28 LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
29 LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
30 LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
31 LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
33 LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
34 LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
35 LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
36 LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
37 LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
38 LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
39 LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
40 LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
44 .macro cache_loop curr, end, line_sz, op
45 10: cache \op, 0(\curr)
46 PTR_ADDU \curr, \curr, \line_sz
50 .macro l1_info sz, line_sz, off
54 mfc0 $1, CP0_CONFIG, 1
56 /* detect line size */
57 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
58 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
62 sllv \line_sz, \sz, \line_sz
64 /* detect associativity */
65 srl \sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF
66 andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHF)
70 mul \sz, \sz, \line_sz
72 /* detect log32(sets) */
73 srl $1, $1, \off + MIPS_CONF1_DS_SHF - MIPS_CONF1_DA_SHF
74 andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHF)
78 /* sz <<= log32(sets) */
88 * mips_cache_reset - low level initialisation of the primary caches
90 * This routine initialises the primary caches to ensure that they have good
91 * parity. It must be called by the ROM before any cached locations are used
92 * to prevent the possibility of data with bad parity being written to memory.
94 * To initialise the instruction cache it is essential that a source of data
95 * with good parity is available. This routine will initialise an area of
96 * memory starting at location zero to be used as a source of parity.
105 LEAF(mips_cache_reset)
106 #ifndef CONFIG_SYS_CACHE_SIZE_AUTO
107 li R_IC_SIZE, CONFIG_SYS_ICACHE_SIZE
108 li R_IC_LINE, CONFIG_SYS_ICACHE_LINE_SIZE
110 l1_info R_IC_SIZE, R_IC_LINE, MIPS_CONF1_IA_SHF
113 #ifndef CONFIG_SYS_CACHE_SIZE_AUTO
114 li R_DC_SIZE, CONFIG_SYS_DCACHE_SIZE
115 li R_DC_LINE, CONFIG_SYS_DCACHE_LINE_SIZE
117 l1_info R_DC_SIZE, R_DC_LINE, MIPS_CONF1_DA_SHF
120 #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
122 /* Determine the largest L1 cache size */
123 #ifndef CONFIG_SYS_CACHE_SIZE_AUTO
124 #if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
125 li v0, CONFIG_SYS_ICACHE_SIZE
127 li v0, CONFIG_SYS_DCACHE_SIZE
131 sltu t1, R_IC_SIZE, R_DC_SIZE
132 movn v0, R_DC_SIZE, t1
135 * Now clear that much memory starting from zero.
140 f_fill64 a0, -64, zero
143 #endif /* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD */
146 * The TagLo registers used depend upon the CPU implementation, but the
147 * architecture requires that it is safe for software to write to both
148 * TagLo selects 0 & 2 covering supported cases.
151 mtc0 zero, CP0_TAGLO, 2
154 * The caches are probably in an indeterminate state, so we force good
155 * parity into them by doing an invalidate for each line. If
156 * CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is set then we'll proceed to
157 * perform a load/fill & a further invalidate for each line, assuming
158 * that the bottom of RAM (having just been cleared) will generate good
159 * parity for the cache.
163 * Initialize the I-cache first,
166 PTR_LI t0, INDEX_BASE
167 PTR_ADDU t1, t0, R_IC_SIZE
168 /* clear tag to invalidate */
169 cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
170 #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
171 /* fill once, so data field parity is correct */
172 PTR_LI t0, INDEX_BASE
173 cache_loop t0, t1, R_IC_LINE, FILL
174 /* invalidate again - prudent but not strictly neccessary */
175 PTR_LI t0, INDEX_BASE
176 cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
179 /* Enable use of the I-cache by setting Config.K0 */
182 li t1, CONFIG_SYS_MIPS_CACHE_MODE
183 #if __mips_isa_rev >= 2
186 ori t0, t0, CONF_CM_CMASK
187 xori t0, t0, CONF_CM_CMASK
193 * then initialize D-cache.
195 1: blez R_DC_SIZE, 3f
196 PTR_LI t0, INDEX_BASE
197 PTR_ADDU t1, t0, R_DC_SIZE
199 cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
200 #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
201 /* load from each line (in cached space) */
202 PTR_LI t0, INDEX_BASE
203 2: LONG_L zero, 0(t0)
204 PTR_ADDU t0, R_DC_LINE
207 PTR_LI t0, INDEX_BASE
208 cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
212 END(mips_cache_reset)
215 * dcache_status - get cache status
217 * RETURNS: 0 - cache disabled; 1 - cache enabled
222 li t1, CONF_CM_UNCACHED
223 andi t0, t0, CONF_CM_CMASK
231 * dcache_disable - disable cache
240 ori t0, t0, CONF_CM_UNCACHED
246 * dcache_enable - enable cache
253 ori t0, CONF_CM_CMASK
254 xori t0, CONF_CM_CMASK
255 ori t0, CONFIG_SYS_MIPS_CACHE_MODE