2 * Cache-handling routined for MIPS CPUs
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm-offsets.h>
12 #include <asm/regdef.h>
13 #include <asm/mipsregs.h>
14 #include <asm/addrspace.h>
15 #include <asm/cacheops.h>
17 #ifndef CONFIG_SYS_MIPS_CACHE_MODE
18 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
27 #define INDEX_BASE CKSEG0
29 .macro f_fill64 dst, offset, val
30 LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
31 LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
32 LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
33 LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
34 LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
35 LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
36 LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
37 LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
39 LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
40 LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
41 LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
42 LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
43 LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
44 LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
45 LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
46 LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
50 .macro cache_loop curr, end, line_sz, op
51 10: cache \op, 0(\curr)
52 PTR_ADDU \curr, \curr, \line_sz
57 * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
59 LEAF(mips_init_icache)
64 /* clear tag to invalidate */
65 cache_loop t0, t1, a2, INDEX_STORE_TAG_I
66 /* fill once, so data field parity is correct */
68 cache_loop t0, t1, a2, FILL
69 /* invalidate again - prudent but not strictly neccessary */
71 cache_loop t0, t1, a2, INDEX_STORE_TAG_I
76 * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
78 LEAF(mips_init_dcache)
84 cache_loop t0, t1, a2, INDEX_STORE_TAG_D
85 /* load from each line (in cached space) */
92 cache_loop t0, t1, a2, INDEX_STORE_TAG_D
96 .macro l1_info sz, line_sz, off
100 mfc0 $1, CP0_CONFIG, 1
102 /* detect line size */
103 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHIFT - MIPS_CONF1_DA_SHIFT
104 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT)
108 sllv \line_sz, \sz, \line_sz
110 /* detect associativity */
111 srl \sz, $1, \off + MIPS_CONF1_DA_SHIFT - MIPS_CONF1_DA_SHIFT
112 andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT)
116 mul \sz, \sz, \line_sz
118 /* detect log32(sets) */
119 srl $1, $1, \off + MIPS_CONF1_DS_SHIFT - MIPS_CONF1_DA_SHIFT
120 andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT)
124 /* sz <<= log32(sets) */
134 * mips_cache_reset - low level initialisation of the primary caches
136 * This routine initialises the primary caches to ensure that they have good
137 * parity. It must be called by the ROM before any cached locations are used
138 * to prevent the possibility of data with bad parity being written to memory.
140 * To initialise the instruction cache it is essential that a source of data
141 * with good parity is available. This routine will initialise an area of
142 * memory starting at location zero to be used as a source of parity.
147 NESTED(mips_cache_reset, 0, ra)
150 #ifdef CONFIG_SYS_ICACHE_SIZE
151 li t2, CONFIG_SYS_ICACHE_SIZE
152 li t8, CONFIG_SYS_CACHELINE_SIZE
154 l1_info t2, t8, MIPS_CONF1_IA_SHIFT
157 #ifdef CONFIG_SYS_DCACHE_SIZE
158 li t3, CONFIG_SYS_DCACHE_SIZE
159 li t9, CONFIG_SYS_CACHELINE_SIZE
161 l1_info t3, t9, MIPS_CONF1_DA_SHIFT
164 /* Determine the largest L1 cache size */
165 #if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
166 #if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
167 li v0, CONFIG_SYS_ICACHE_SIZE
169 li v0, CONFIG_SYS_DCACHE_SIZE
177 * Now clear that much memory starting from zero.
182 f_fill64 a0, -64, zero
186 * The caches are probably in an indeterminate state,
187 * so we force good parity into them by doing an
188 * invalidate, load/fill, invalidate for each line.
192 * Assume bottom of RAM will generate good parity for the cache.
196 * Initialize the I-cache first,
200 PTR_LA v1, mips_init_icache
204 * then initialize D-cache.
208 PTR_LA v1, mips_init_dcache
212 END(mips_cache_reset)
215 * dcache_status - get cache status
217 * RETURNS: 0 - cache disabled; 1 - cache enabled
222 li t1, CONF_CM_UNCACHED
223 andi t0, t0, CONF_CM_CMASK
231 * dcache_disable - disable cache
240 ori t0, t0, CONF_CM_UNCACHED
246 * dcache_enable - enable cache
253 ori t0, CONF_CM_CMASK
254 xori t0, CONF_CM_CMASK
255 ori t0, CONFIG_SYS_MIPS_CACHE_MODE