1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
9 #include <asm/cacheops.h>
10 #ifdef CONFIG_MIPS_L2_CACHE
14 #include <asm/mipsregs.h>
15 #include <asm/system.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 static void probe_l2(void)
21 #ifdef CONFIG_MIPS_L2_CACHE
22 unsigned long conf2, sl;
25 if (!(read_c0_config1() & MIPS_CONF_M))
28 conf2 = read_c0_config2();
30 if (__mips_isa_rev >= 6) {
31 l2c = conf2 & MIPS_CONF_M;
33 l2c = read_c0_config3() & MIPS_CONF_M;
35 l2c = read_c0_config4() & MIPS_CONF_M;
37 l2c = read_c0_config5() & MIPS_CONF5_L2C;
40 if (l2c && config_enabled(CONFIG_MIPS_CM)) {
41 gd->arch.l2_line_size = mips_cm_l2_line_size();
43 /* We don't know how to retrieve L2 config on this system */
46 sl = (conf2 & MIPS_CONF2_SL) >> MIPS_CONF2_SL_SHF;
47 gd->arch.l2_line_size = sl ? (2 << sl) : 0;
52 void mips_cache_probe(void)
54 #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
55 unsigned long conf1, il, dl;
57 conf1 = read_c0_config1();
59 il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
60 dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
62 gd->arch.l1i_line_size = il ? (2 << il) : 0;
63 gd->arch.l1d_line_size = dl ? (2 << dl) : 0;
68 static inline unsigned long icache_line_size(void)
70 #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
71 return gd->arch.l1i_line_size;
73 return CONFIG_SYS_ICACHE_LINE_SIZE;
77 static inline unsigned long dcache_line_size(void)
79 #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
80 return gd->arch.l1d_line_size;
82 return CONFIG_SYS_DCACHE_LINE_SIZE;
86 static inline unsigned long scache_line_size(void)
88 #ifdef CONFIG_MIPS_L2_CACHE
89 return gd->arch.l2_line_size;
91 return CONFIG_SYS_SCACHE_LINE_SIZE;
95 #define cache_loop(start, end, lsize, ops...) do { \
96 const void *addr = (const void *)(start & ~(lsize - 1)); \
97 const void *aend = (const void *)((end - 1) & ~(lsize - 1)); \
98 const unsigned int cache_ops[] = { ops }; \
104 for (; addr <= aend; addr += lsize) { \
105 for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \
106 mips_cache(cache_ops[i], addr); \
110 void flush_cache(ulong start_addr, ulong size)
112 unsigned long ilsize = icache_line_size();
113 unsigned long dlsize = dcache_line_size();
114 unsigned long slsize = scache_line_size();
116 /* aend will be miscalculated when size is zero, so we return here */
120 if ((ilsize == dlsize) && !slsize) {
121 /* flush I-cache & D-cache simultaneously */
122 cache_loop(start_addr, start_addr + size, ilsize,
123 HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
128 cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
131 cache_loop(start_addr, start_addr + size, slsize, HIT_WRITEBACK_INV_SD);
134 cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
137 /* ensure cache ops complete before any further memory accesses */
140 /* ensure the pipeline doesn't contain now-invalid instructions */
141 instruction_hazard_barrier();
144 void flush_dcache_range(ulong start_addr, ulong stop)
146 unsigned long lsize = dcache_line_size();
147 unsigned long slsize = scache_line_size();
149 /* aend will be miscalculated when size is zero, so we return here */
150 if (start_addr == stop)
153 cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
156 cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD);
158 /* ensure cache ops complete before any further memory accesses */
162 void invalidate_dcache_range(ulong start_addr, ulong stop)
164 unsigned long lsize = dcache_line_size();
165 unsigned long slsize = scache_line_size();
167 /* aend will be miscalculated when size is zero, so we return here */
168 if (start_addr == stop)
171 /* invalidate L2 cache */
172 cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD);
174 cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
176 /* ensure cache ops complete before any further memory accesses */
180 int dcache_status(void)
182 unsigned int cca = read_c0_config() & CONF_CM_CMASK;
183 return cca != CONF_CM_UNCACHED;
186 void dcache_enable(void)
188 puts("Not supported!\n");
191 void dcache_disable(void)
193 /* change CCA to uncached */
194 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
196 /* ensure the pipeline doesn't contain now-invalid instructions */
197 instruction_hazard_barrier();