1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_PCSXX_DEFS_H__
29 #define __CVMX_PCSXX_DEFS_H__
31 static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id)
33 switch (cvmx_get_octeon_family()) {
34 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
35 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
36 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
37 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
38 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
39 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
40 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
41 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
42 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
44 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
47 static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id)
49 switch (cvmx_get_octeon_family()) {
50 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
51 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
52 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
53 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
54 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
55 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
56 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
57 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
58 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
60 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
63 static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id)
65 switch (cvmx_get_octeon_family()) {
66 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
67 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
68 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
69 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
70 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
71 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
72 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
73 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
74 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
76 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
79 static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id)
81 switch (cvmx_get_octeon_family()) {
82 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
83 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
84 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
85 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
86 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
87 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
88 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
89 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
90 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
92 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
95 static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id)
97 switch (cvmx_get_octeon_family()) {
98 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
99 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
100 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
101 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
102 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
103 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
104 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
105 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
106 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
108 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
111 static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id)
113 switch (cvmx_get_octeon_family()) {
114 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
115 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
116 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
117 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
118 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
119 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
120 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
121 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
122 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
124 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
127 static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id)
129 switch (cvmx_get_octeon_family()) {
130 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
131 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
132 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
133 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
134 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
135 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
136 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
137 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
138 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
140 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
143 static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id)
145 switch (cvmx_get_octeon_family()) {
146 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
147 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
148 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
149 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
150 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
151 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
152 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
153 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
154 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
156 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
159 static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id)
161 switch (cvmx_get_octeon_family()) {
162 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
163 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
164 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
165 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
166 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
167 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
168 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
169 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
170 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
172 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
175 static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id)
177 switch (cvmx_get_octeon_family()) {
178 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
179 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
180 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
181 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
182 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
183 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
184 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
185 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
186 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
188 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
191 static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id)
193 switch (cvmx_get_octeon_family()) {
194 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
195 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
196 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
197 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
198 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
199 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
200 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
201 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
202 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
204 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
207 static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id)
209 switch (cvmx_get_octeon_family()) {
210 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
211 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
212 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
213 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
214 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
215 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
216 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
217 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
218 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
220 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
223 static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id)
225 switch (cvmx_get_octeon_family()) {
226 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
227 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
228 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
229 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
230 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
231 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
232 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
233 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
234 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
236 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
239 static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id)
241 switch (cvmx_get_octeon_family()) {
242 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
243 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
244 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
245 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
246 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
247 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
248 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
249 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
250 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
252 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
255 static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
257 switch (cvmx_get_octeon_family()) {
258 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
259 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
260 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
261 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
262 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
263 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
264 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
265 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
266 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
268 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
271 union cvmx_pcsxx_10gbx_status_reg {
273 struct cvmx_pcsxx_10gbx_status_reg_s {
274 #ifdef __BIG_ENDIAN_BITFIELD
275 uint64_t reserved_13_63:51;
278 uint64_t reserved_4_10:7;
288 uint64_t reserved_4_10:7;
291 uint64_t reserved_13_63:51;
294 struct cvmx_pcsxx_10gbx_status_reg_s cn52xx;
295 struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1;
296 struct cvmx_pcsxx_10gbx_status_reg_s cn56xx;
297 struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1;
298 struct cvmx_pcsxx_10gbx_status_reg_s cn61xx;
299 struct cvmx_pcsxx_10gbx_status_reg_s cn63xx;
300 struct cvmx_pcsxx_10gbx_status_reg_s cn63xxp1;
301 struct cvmx_pcsxx_10gbx_status_reg_s cn66xx;
302 struct cvmx_pcsxx_10gbx_status_reg_s cn68xx;
303 struct cvmx_pcsxx_10gbx_status_reg_s cn68xxp1;
306 union cvmx_pcsxx_bist_status_reg {
308 struct cvmx_pcsxx_bist_status_reg_s {
309 #ifdef __BIG_ENDIAN_BITFIELD
310 uint64_t reserved_1_63:63;
311 uint64_t bist_status:1;
313 uint64_t bist_status:1;
314 uint64_t reserved_1_63:63;
317 struct cvmx_pcsxx_bist_status_reg_s cn52xx;
318 struct cvmx_pcsxx_bist_status_reg_s cn52xxp1;
319 struct cvmx_pcsxx_bist_status_reg_s cn56xx;
320 struct cvmx_pcsxx_bist_status_reg_s cn56xxp1;
321 struct cvmx_pcsxx_bist_status_reg_s cn61xx;
322 struct cvmx_pcsxx_bist_status_reg_s cn63xx;
323 struct cvmx_pcsxx_bist_status_reg_s cn63xxp1;
324 struct cvmx_pcsxx_bist_status_reg_s cn66xx;
325 struct cvmx_pcsxx_bist_status_reg_s cn68xx;
326 struct cvmx_pcsxx_bist_status_reg_s cn68xxp1;
329 union cvmx_pcsxx_bit_lock_status_reg {
331 struct cvmx_pcsxx_bit_lock_status_reg_s {
332 #ifdef __BIG_ENDIAN_BITFIELD
333 uint64_t reserved_4_63:60;
343 uint64_t reserved_4_63:60;
346 struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx;
347 struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1;
348 struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx;
349 struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1;
350 struct cvmx_pcsxx_bit_lock_status_reg_s cn61xx;
351 struct cvmx_pcsxx_bit_lock_status_reg_s cn63xx;
352 struct cvmx_pcsxx_bit_lock_status_reg_s cn63xxp1;
353 struct cvmx_pcsxx_bit_lock_status_reg_s cn66xx;
354 struct cvmx_pcsxx_bit_lock_status_reg_s cn68xx;
355 struct cvmx_pcsxx_bit_lock_status_reg_s cn68xxp1;
358 union cvmx_pcsxx_control1_reg {
360 struct cvmx_pcsxx_control1_reg_s {
361 #ifdef __BIG_ENDIAN_BITFIELD
362 uint64_t reserved_16_63:48;
366 uint64_t reserved_12_12:1;
368 uint64_t reserved_7_10:4;
371 uint64_t reserved_0_1:2;
373 uint64_t reserved_0_1:2;
376 uint64_t reserved_7_10:4;
378 uint64_t reserved_12_12:1;
382 uint64_t reserved_16_63:48;
385 struct cvmx_pcsxx_control1_reg_s cn52xx;
386 struct cvmx_pcsxx_control1_reg_s cn52xxp1;
387 struct cvmx_pcsxx_control1_reg_s cn56xx;
388 struct cvmx_pcsxx_control1_reg_s cn56xxp1;
389 struct cvmx_pcsxx_control1_reg_s cn61xx;
390 struct cvmx_pcsxx_control1_reg_s cn63xx;
391 struct cvmx_pcsxx_control1_reg_s cn63xxp1;
392 struct cvmx_pcsxx_control1_reg_s cn66xx;
393 struct cvmx_pcsxx_control1_reg_s cn68xx;
394 struct cvmx_pcsxx_control1_reg_s cn68xxp1;
397 union cvmx_pcsxx_control2_reg {
399 struct cvmx_pcsxx_control2_reg_s {
400 #ifdef __BIG_ENDIAN_BITFIELD
401 uint64_t reserved_2_63:62;
405 uint64_t reserved_2_63:62;
408 struct cvmx_pcsxx_control2_reg_s cn52xx;
409 struct cvmx_pcsxx_control2_reg_s cn52xxp1;
410 struct cvmx_pcsxx_control2_reg_s cn56xx;
411 struct cvmx_pcsxx_control2_reg_s cn56xxp1;
412 struct cvmx_pcsxx_control2_reg_s cn61xx;
413 struct cvmx_pcsxx_control2_reg_s cn63xx;
414 struct cvmx_pcsxx_control2_reg_s cn63xxp1;
415 struct cvmx_pcsxx_control2_reg_s cn66xx;
416 struct cvmx_pcsxx_control2_reg_s cn68xx;
417 struct cvmx_pcsxx_control2_reg_s cn68xxp1;
420 union cvmx_pcsxx_int_en_reg {
422 struct cvmx_pcsxx_int_en_reg_s {
423 #ifdef __BIG_ENDIAN_BITFIELD
424 uint64_t reserved_7_63:57;
425 uint64_t dbg_sync_en:1;
426 uint64_t algnlos_en:1;
427 uint64_t synlos_en:1;
428 uint64_t bitlckls_en:1;
429 uint64_t rxsynbad_en:1;
435 uint64_t rxsynbad_en:1;
436 uint64_t bitlckls_en:1;
437 uint64_t synlos_en:1;
438 uint64_t algnlos_en:1;
439 uint64_t dbg_sync_en:1;
440 uint64_t reserved_7_63:57;
443 struct cvmx_pcsxx_int_en_reg_cn52xx {
444 #ifdef __BIG_ENDIAN_BITFIELD
445 uint64_t reserved_6_63:58;
446 uint64_t algnlos_en:1;
447 uint64_t synlos_en:1;
448 uint64_t bitlckls_en:1;
449 uint64_t rxsynbad_en:1;
455 uint64_t rxsynbad_en:1;
456 uint64_t bitlckls_en:1;
457 uint64_t synlos_en:1;
458 uint64_t algnlos_en:1;
459 uint64_t reserved_6_63:58;
462 struct cvmx_pcsxx_int_en_reg_cn52xx cn52xxp1;
463 struct cvmx_pcsxx_int_en_reg_cn52xx cn56xx;
464 struct cvmx_pcsxx_int_en_reg_cn52xx cn56xxp1;
465 struct cvmx_pcsxx_int_en_reg_s cn61xx;
466 struct cvmx_pcsxx_int_en_reg_s cn63xx;
467 struct cvmx_pcsxx_int_en_reg_s cn63xxp1;
468 struct cvmx_pcsxx_int_en_reg_s cn66xx;
469 struct cvmx_pcsxx_int_en_reg_s cn68xx;
470 struct cvmx_pcsxx_int_en_reg_s cn68xxp1;
473 union cvmx_pcsxx_int_reg {
475 struct cvmx_pcsxx_int_reg_s {
476 #ifdef __BIG_ENDIAN_BITFIELD
477 uint64_t reserved_7_63:57;
493 uint64_t reserved_7_63:57;
496 struct cvmx_pcsxx_int_reg_cn52xx {
497 #ifdef __BIG_ENDIAN_BITFIELD
498 uint64_t reserved_6_63:58;
512 uint64_t reserved_6_63:58;
515 struct cvmx_pcsxx_int_reg_cn52xx cn52xxp1;
516 struct cvmx_pcsxx_int_reg_cn52xx cn56xx;
517 struct cvmx_pcsxx_int_reg_cn52xx cn56xxp1;
518 struct cvmx_pcsxx_int_reg_s cn61xx;
519 struct cvmx_pcsxx_int_reg_s cn63xx;
520 struct cvmx_pcsxx_int_reg_s cn63xxp1;
521 struct cvmx_pcsxx_int_reg_s cn66xx;
522 struct cvmx_pcsxx_int_reg_s cn68xx;
523 struct cvmx_pcsxx_int_reg_s cn68xxp1;
526 union cvmx_pcsxx_log_anl_reg {
528 struct cvmx_pcsxx_log_anl_reg_s {
529 #ifdef __BIG_ENDIAN_BITFIELD
530 uint64_t reserved_7_63:57;
533 uint64_t lafifovfl:1;
539 uint64_t lafifovfl:1;
542 uint64_t reserved_7_63:57;
545 struct cvmx_pcsxx_log_anl_reg_s cn52xx;
546 struct cvmx_pcsxx_log_anl_reg_s cn52xxp1;
547 struct cvmx_pcsxx_log_anl_reg_s cn56xx;
548 struct cvmx_pcsxx_log_anl_reg_s cn56xxp1;
549 struct cvmx_pcsxx_log_anl_reg_s cn61xx;
550 struct cvmx_pcsxx_log_anl_reg_s cn63xx;
551 struct cvmx_pcsxx_log_anl_reg_s cn63xxp1;
552 struct cvmx_pcsxx_log_anl_reg_s cn66xx;
553 struct cvmx_pcsxx_log_anl_reg_s cn68xx;
554 struct cvmx_pcsxx_log_anl_reg_s cn68xxp1;
557 union cvmx_pcsxx_misc_ctl_reg {
559 struct cvmx_pcsxx_misc_ctl_reg_s {
560 #ifdef __BIG_ENDIAN_BITFIELD
561 uint64_t reserved_4_63:60;
571 uint64_t reserved_4_63:60;
574 struct cvmx_pcsxx_misc_ctl_reg_s cn52xx;
575 struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1;
576 struct cvmx_pcsxx_misc_ctl_reg_s cn56xx;
577 struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1;
578 struct cvmx_pcsxx_misc_ctl_reg_s cn61xx;
579 struct cvmx_pcsxx_misc_ctl_reg_s cn63xx;
580 struct cvmx_pcsxx_misc_ctl_reg_s cn63xxp1;
581 struct cvmx_pcsxx_misc_ctl_reg_s cn66xx;
582 struct cvmx_pcsxx_misc_ctl_reg_s cn68xx;
583 struct cvmx_pcsxx_misc_ctl_reg_s cn68xxp1;
586 union cvmx_pcsxx_rx_sync_states_reg {
588 struct cvmx_pcsxx_rx_sync_states_reg_s {
589 #ifdef __BIG_ENDIAN_BITFIELD
590 uint64_t reserved_16_63:48;
600 uint64_t reserved_16_63:48;
603 struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx;
604 struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1;
605 struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx;
606 struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1;
607 struct cvmx_pcsxx_rx_sync_states_reg_s cn61xx;
608 struct cvmx_pcsxx_rx_sync_states_reg_s cn63xx;
609 struct cvmx_pcsxx_rx_sync_states_reg_s cn63xxp1;
610 struct cvmx_pcsxx_rx_sync_states_reg_s cn66xx;
611 struct cvmx_pcsxx_rx_sync_states_reg_s cn68xx;
612 struct cvmx_pcsxx_rx_sync_states_reg_s cn68xxp1;
615 union cvmx_pcsxx_spd_abil_reg {
617 struct cvmx_pcsxx_spd_abil_reg_s {
618 #ifdef __BIG_ENDIAN_BITFIELD
619 uint64_t reserved_2_63:62;
625 uint64_t reserved_2_63:62;
628 struct cvmx_pcsxx_spd_abil_reg_s cn52xx;
629 struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1;
630 struct cvmx_pcsxx_spd_abil_reg_s cn56xx;
631 struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1;
632 struct cvmx_pcsxx_spd_abil_reg_s cn61xx;
633 struct cvmx_pcsxx_spd_abil_reg_s cn63xx;
634 struct cvmx_pcsxx_spd_abil_reg_s cn63xxp1;
635 struct cvmx_pcsxx_spd_abil_reg_s cn66xx;
636 struct cvmx_pcsxx_spd_abil_reg_s cn68xx;
637 struct cvmx_pcsxx_spd_abil_reg_s cn68xxp1;
640 union cvmx_pcsxx_status1_reg {
642 struct cvmx_pcsxx_status1_reg_s {
643 #ifdef __BIG_ENDIAN_BITFIELD
644 uint64_t reserved_8_63:56;
646 uint64_t reserved_3_6:4;
649 uint64_t reserved_0_0:1;
651 uint64_t reserved_0_0:1;
654 uint64_t reserved_3_6:4;
656 uint64_t reserved_8_63:56;
659 struct cvmx_pcsxx_status1_reg_s cn52xx;
660 struct cvmx_pcsxx_status1_reg_s cn52xxp1;
661 struct cvmx_pcsxx_status1_reg_s cn56xx;
662 struct cvmx_pcsxx_status1_reg_s cn56xxp1;
663 struct cvmx_pcsxx_status1_reg_s cn61xx;
664 struct cvmx_pcsxx_status1_reg_s cn63xx;
665 struct cvmx_pcsxx_status1_reg_s cn63xxp1;
666 struct cvmx_pcsxx_status1_reg_s cn66xx;
667 struct cvmx_pcsxx_status1_reg_s cn68xx;
668 struct cvmx_pcsxx_status1_reg_s cn68xxp1;
671 union cvmx_pcsxx_status2_reg {
673 struct cvmx_pcsxx_status2_reg_s {
674 #ifdef __BIG_ENDIAN_BITFIELD
675 uint64_t reserved_16_63:48;
677 uint64_t reserved_12_13:2;
680 uint64_t reserved_3_9:7;
688 uint64_t reserved_3_9:7;
691 uint64_t reserved_12_13:2;
693 uint64_t reserved_16_63:48;
696 struct cvmx_pcsxx_status2_reg_s cn52xx;
697 struct cvmx_pcsxx_status2_reg_s cn52xxp1;
698 struct cvmx_pcsxx_status2_reg_s cn56xx;
699 struct cvmx_pcsxx_status2_reg_s cn56xxp1;
700 struct cvmx_pcsxx_status2_reg_s cn61xx;
701 struct cvmx_pcsxx_status2_reg_s cn63xx;
702 struct cvmx_pcsxx_status2_reg_s cn63xxp1;
703 struct cvmx_pcsxx_status2_reg_s cn66xx;
704 struct cvmx_pcsxx_status2_reg_s cn68xx;
705 struct cvmx_pcsxx_status2_reg_s cn68xxp1;
708 union cvmx_pcsxx_tx_rx_polarity_reg {
710 struct cvmx_pcsxx_tx_rx_polarity_reg_s {
711 #ifdef __BIG_ENDIAN_BITFIELD
712 uint64_t reserved_10_63:54;
713 uint64_t xor_rxplrt:4;
714 uint64_t xor_txplrt:4;
720 uint64_t xor_txplrt:4;
721 uint64_t xor_rxplrt:4;
722 uint64_t reserved_10_63:54;
725 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx;
726 struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 {
727 #ifdef __BIG_ENDIAN_BITFIELD
728 uint64_t reserved_2_63:62;
734 uint64_t reserved_2_63:62;
737 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx;
738 struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1;
739 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn61xx;
740 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xx;
741 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xxp1;
742 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn66xx;
743 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xx;
744 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xxp1;
747 union cvmx_pcsxx_tx_rx_states_reg {
749 struct cvmx_pcsxx_tx_rx_states_reg_s {
750 #ifdef __BIG_ENDIAN_BITFIELD
751 uint64_t reserved_14_63:50;
771 uint64_t reserved_14_63:50;
774 struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx;
775 struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 {
776 #ifdef __BIG_ENDIAN_BITFIELD
777 uint64_t reserved_13_63:51;
795 uint64_t reserved_13_63:51;
798 struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx;
799 struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1;
800 struct cvmx_pcsxx_tx_rx_states_reg_s cn61xx;
801 struct cvmx_pcsxx_tx_rx_states_reg_s cn63xx;
802 struct cvmx_pcsxx_tx_rx_states_reg_s cn63xxp1;
803 struct cvmx_pcsxx_tx_rx_states_reg_s cn66xx;
804 struct cvmx_pcsxx_tx_rx_states_reg_s cn68xx;
805 struct cvmx_pcsxx_tx_rx_states_reg_s cn68xxp1;