1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (C) 2003-2018 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_PCSXX_DEFS_H__
29 #define __CVMX_PCSXX_DEFS_H__
31 static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id)
33 switch (cvmx_get_octeon_family()) {
34 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
35 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
36 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
37 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
38 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
39 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
40 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
41 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
42 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
44 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
47 static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id)
49 switch (cvmx_get_octeon_family()) {
50 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
51 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
52 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
53 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
54 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
55 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
56 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
57 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
58 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
60 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
63 static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id)
65 switch (cvmx_get_octeon_family()) {
66 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
67 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
68 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
69 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
70 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
71 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
72 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
73 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
74 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
76 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
79 static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id)
81 switch (cvmx_get_octeon_family()) {
82 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
83 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
84 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
85 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
86 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
87 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
88 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
89 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
90 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
92 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
95 static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id)
97 switch (cvmx_get_octeon_family()) {
98 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
99 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
100 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
101 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
102 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
103 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
104 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
105 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
106 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
108 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
111 static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id)
113 switch (cvmx_get_octeon_family()) {
114 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
115 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
116 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
117 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
118 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
119 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
120 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
121 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
122 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
124 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
127 static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id)
129 switch (cvmx_get_octeon_family()) {
130 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
131 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
132 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
133 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
134 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
135 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
136 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
137 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
138 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
140 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
143 static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id)
145 switch (cvmx_get_octeon_family()) {
146 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
147 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
148 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
149 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
150 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
151 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
152 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
153 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
154 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
156 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
159 static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id)
161 switch (cvmx_get_octeon_family()) {
162 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
163 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
164 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
165 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
166 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
167 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
168 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
169 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
170 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
172 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
175 static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id)
177 switch (cvmx_get_octeon_family()) {
178 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
179 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
180 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
181 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
182 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
183 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
184 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
185 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
186 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
188 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
191 static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id)
193 switch (cvmx_get_octeon_family()) {
194 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
195 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
196 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
197 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
198 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
199 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
200 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
201 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
202 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
204 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
207 static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id)
209 switch (cvmx_get_octeon_family()) {
210 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
211 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
212 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
213 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
214 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
215 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
216 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
217 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
218 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
220 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
223 static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id)
225 switch (cvmx_get_octeon_family()) {
226 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
227 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
228 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
229 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
230 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
231 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
232 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
233 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
234 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
236 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
239 static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id)
241 switch (cvmx_get_octeon_family()) {
242 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
243 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
244 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
245 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
246 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
247 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
248 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
249 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
250 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
252 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
255 static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
257 switch (cvmx_get_octeon_family()) {
258 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
259 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
260 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
261 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
262 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
263 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
264 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
265 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
266 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
268 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
271 void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
273 union cvmx_pcsxx_10gbx_status_reg {
275 struct cvmx_pcsxx_10gbx_status_reg_s {
276 #ifdef __BIG_ENDIAN_BITFIELD
277 uint64_t reserved_13_63:51;
280 uint64_t reserved_4_10:7;
290 uint64_t reserved_4_10:7;
293 uint64_t reserved_13_63:51;
298 union cvmx_pcsxx_bist_status_reg {
300 struct cvmx_pcsxx_bist_status_reg_s {
301 #ifdef __BIG_ENDIAN_BITFIELD
302 uint64_t reserved_1_63:63;
303 uint64_t bist_status:1;
305 uint64_t bist_status:1;
306 uint64_t reserved_1_63:63;
311 union cvmx_pcsxx_bit_lock_status_reg {
313 struct cvmx_pcsxx_bit_lock_status_reg_s {
314 #ifdef __BIG_ENDIAN_BITFIELD
315 uint64_t reserved_4_63:60;
325 uint64_t reserved_4_63:60;
330 union cvmx_pcsxx_control1_reg {
332 struct cvmx_pcsxx_control1_reg_s {
333 #ifdef __BIG_ENDIAN_BITFIELD
334 uint64_t reserved_16_63:48;
338 uint64_t reserved_12_12:1;
340 uint64_t reserved_7_10:4;
343 uint64_t reserved_0_1:2;
345 uint64_t reserved_0_1:2;
348 uint64_t reserved_7_10:4;
350 uint64_t reserved_12_12:1;
354 uint64_t reserved_16_63:48;
359 union cvmx_pcsxx_control2_reg {
361 struct cvmx_pcsxx_control2_reg_s {
362 #ifdef __BIG_ENDIAN_BITFIELD
363 uint64_t reserved_2_63:62;
367 uint64_t reserved_2_63:62;
372 union cvmx_pcsxx_int_en_reg {
374 struct cvmx_pcsxx_int_en_reg_s {
375 #ifdef __BIG_ENDIAN_BITFIELD
376 uint64_t reserved_7_63:57;
377 uint64_t dbg_sync_en:1;
378 uint64_t algnlos_en:1;
379 uint64_t synlos_en:1;
380 uint64_t bitlckls_en:1;
381 uint64_t rxsynbad_en:1;
387 uint64_t rxsynbad_en:1;
388 uint64_t bitlckls_en:1;
389 uint64_t synlos_en:1;
390 uint64_t algnlos_en:1;
391 uint64_t dbg_sync_en:1;
392 uint64_t reserved_7_63:57;
395 struct cvmx_pcsxx_int_en_reg_cn52xx {
396 #ifdef __BIG_ENDIAN_BITFIELD
397 uint64_t reserved_6_63:58;
398 uint64_t algnlos_en:1;
399 uint64_t synlos_en:1;
400 uint64_t bitlckls_en:1;
401 uint64_t rxsynbad_en:1;
407 uint64_t rxsynbad_en:1;
408 uint64_t bitlckls_en:1;
409 uint64_t synlos_en:1;
410 uint64_t algnlos_en:1;
411 uint64_t reserved_6_63:58;
416 union cvmx_pcsxx_int_reg {
418 struct cvmx_pcsxx_int_reg_s {
419 #ifdef __BIG_ENDIAN_BITFIELD
420 uint64_t reserved_7_63:57;
436 uint64_t reserved_7_63:57;
439 struct cvmx_pcsxx_int_reg_cn52xx {
440 #ifdef __BIG_ENDIAN_BITFIELD
441 uint64_t reserved_6_63:58;
455 uint64_t reserved_6_63:58;
460 union cvmx_pcsxx_log_anl_reg {
462 struct cvmx_pcsxx_log_anl_reg_s {
463 #ifdef __BIG_ENDIAN_BITFIELD
464 uint64_t reserved_7_63:57;
467 uint64_t lafifovfl:1;
473 uint64_t lafifovfl:1;
476 uint64_t reserved_7_63:57;
481 union cvmx_pcsxx_misc_ctl_reg {
483 struct cvmx_pcsxx_misc_ctl_reg_s {
484 #ifdef __BIG_ENDIAN_BITFIELD
485 uint64_t reserved_4_63:60;
495 uint64_t reserved_4_63:60;
500 union cvmx_pcsxx_rx_sync_states_reg {
502 struct cvmx_pcsxx_rx_sync_states_reg_s {
503 #ifdef __BIG_ENDIAN_BITFIELD
504 uint64_t reserved_16_63:48;
514 uint64_t reserved_16_63:48;
519 union cvmx_pcsxx_spd_abil_reg {
521 struct cvmx_pcsxx_spd_abil_reg_s {
522 #ifdef __BIG_ENDIAN_BITFIELD
523 uint64_t reserved_2_63:62;
529 uint64_t reserved_2_63:62;
534 union cvmx_pcsxx_status1_reg {
536 struct cvmx_pcsxx_status1_reg_s {
537 #ifdef __BIG_ENDIAN_BITFIELD
538 uint64_t reserved_8_63:56;
540 uint64_t reserved_3_6:4;
543 uint64_t reserved_0_0:1;
545 uint64_t reserved_0_0:1;
548 uint64_t reserved_3_6:4;
550 uint64_t reserved_8_63:56;
555 union cvmx_pcsxx_status2_reg {
557 struct cvmx_pcsxx_status2_reg_s {
558 #ifdef __BIG_ENDIAN_BITFIELD
559 uint64_t reserved_16_63:48;
561 uint64_t reserved_12_13:2;
564 uint64_t reserved_3_9:7;
572 uint64_t reserved_3_9:7;
575 uint64_t reserved_12_13:2;
577 uint64_t reserved_16_63:48;
582 union cvmx_pcsxx_tx_rx_polarity_reg {
584 struct cvmx_pcsxx_tx_rx_polarity_reg_s {
585 #ifdef __BIG_ENDIAN_BITFIELD
586 uint64_t reserved_10_63:54;
587 uint64_t xor_rxplrt:4;
588 uint64_t xor_txplrt:4;
594 uint64_t xor_txplrt:4;
595 uint64_t xor_rxplrt:4;
596 uint64_t reserved_10_63:54;
599 struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 {
600 #ifdef __BIG_ENDIAN_BITFIELD
601 uint64_t reserved_2_63:62;
607 uint64_t reserved_2_63:62;
612 union cvmx_pcsxx_tx_rx_states_reg {
614 struct cvmx_pcsxx_tx_rx_states_reg_s {
615 #ifdef __BIG_ENDIAN_BITFIELD
616 uint64_t reserved_14_63:50;
636 uint64_t reserved_14_63:50;
639 struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 {
640 #ifdef __BIG_ENDIAN_BITFIELD
641 uint64_t reserved_13_63:51;
659 uint64_t reserved_13_63:51;