arch/mips/include/asm/octeon/cvmx-led-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2012 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
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  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
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  22  * or visit http://www.gnu.org/licenses/.
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  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_LED_DEFS_H__
  29 #define __CVMX_LED_DEFS_H__
  30
  31 #define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull))
  32 #define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull))
  33 #define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull))
  34 #define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull))
  35 #define CVMX_LED_EN (CVMX_ADD_IO_SEG(0x0001180000001A00ull))
  36 #define CVMX_LED_POLARITY (CVMX_ADD_IO_SEG(0x0001180000001A50ull))
  37 #define CVMX_LED_PRT (CVMX_ADD_IO_SEG(0x0001180000001A10ull))
  38 #define CVMX_LED_PRT_FMT (CVMX_ADD_IO_SEG(0x0001180000001A30ull))
  39 #define CVMX_LED_PRT_STATUSX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8)
  40 #define CVMX_LED_UDD_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8)
  41 #define CVMX_LED_UDD_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8)
  42 #define CVMX_LED_UDD_DAT_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16)
  43 #define CVMX_LED_UDD_DAT_SETX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16)
  44
  45 union cvmx_led_blink {
  46         uint64_t u64;
  47         struct cvmx_led_blink_s {
  48 #ifdef __BIG_ENDIAN_BITFIELD
  49                 uint64_t reserved_8_63:56;
  50                 uint64_t rate:8;
  51 #else
  52                 uint64_t rate:8;
  53                 uint64_t reserved_8_63:56;
  54 #endif
  55         } s;
  56 };
  57
  58 union cvmx_led_clk_phase {
  59         uint64_t u64;
  60         struct cvmx_led_clk_phase_s {
  61 #ifdef __BIG_ENDIAN_BITFIELD
  62                 uint64_t reserved_7_63:57;
  63                 uint64_t phase:7;
  64 #else
  65                 uint64_t phase:7;
  66                 uint64_t reserved_7_63:57;
  67 #endif
  68         } s;
  69 };
  70
  71 union cvmx_led_cylon {
  72         uint64_t u64;
  73         struct cvmx_led_cylon_s {
  74 #ifdef __BIG_ENDIAN_BITFIELD
  75                 uint64_t reserved_16_63:48;
  76                 uint64_t rate:16;
  77 #else
  78                 uint64_t rate:16;
  79                 uint64_t reserved_16_63:48;
  80 #endif
  81         } s;
  82 };
  83
  84 union cvmx_led_dbg {
  85         uint64_t u64;
  86         struct cvmx_led_dbg_s {
  87 #ifdef __BIG_ENDIAN_BITFIELD
  88                 uint64_t reserved_1_63:63;
  89                 uint64_t dbg_en:1;
  90 #else
  91                 uint64_t dbg_en:1;
  92                 uint64_t reserved_1_63:63;
  93 #endif
  94         } s;
  95 };
  96
  97 union cvmx_led_en {
  98         uint64_t u64;
  99         struct cvmx_led_en_s {
 100 #ifdef __BIG_ENDIAN_BITFIELD
 101                 uint64_t reserved_1_63:63;
 102                 uint64_t en:1;
 103 #else
 104                 uint64_t en:1;
 105                 uint64_t reserved_1_63:63;
 106 #endif
 107         } s;
 108 };
 109
 110 union cvmx_led_polarity {
 111         uint64_t u64;
 112         struct cvmx_led_polarity_s {
 113 #ifdef __BIG_ENDIAN_BITFIELD
 114                 uint64_t reserved_1_63:63;
 115                 uint64_t polarity:1;
 116 #else
 117                 uint64_t polarity:1;
 118                 uint64_t reserved_1_63:63;
 119 #endif
 120         } s;
 121 };
 122
 123 union cvmx_led_prt {
 124         uint64_t u64;
 125         struct cvmx_led_prt_s {
 126 #ifdef __BIG_ENDIAN_BITFIELD
 127                 uint64_t reserved_8_63:56;
 128                 uint64_t prt_en:8;
 129 #else
 130                 uint64_t prt_en:8;
 131                 uint64_t reserved_8_63:56;
 132 #endif
 133         } s;
 134 };
 135
 136 union cvmx_led_prt_fmt {
 137         uint64_t u64;
 138         struct cvmx_led_prt_fmt_s {
 139 #ifdef __BIG_ENDIAN_BITFIELD
 140                 uint64_t reserved_4_63:60;
 141                 uint64_t format:4;
 142 #else
 143                 uint64_t format:4;
 144                 uint64_t reserved_4_63:60;
 145 #endif
 146         } s;
 147 };
 148
 149 union cvmx_led_prt_statusx {
 150         uint64_t u64;
 151         struct cvmx_led_prt_statusx_s {
 152 #ifdef __BIG_ENDIAN_BITFIELD
 153                 uint64_t reserved_6_63:58;
 154                 uint64_t status:6;
 155 #else
 156                 uint64_t status:6;
 157                 uint64_t reserved_6_63:58;
 158 #endif
 159         } s;
 160 };
 161
 162 union cvmx_led_udd_cntx {
 163         uint64_t u64;
 164         struct cvmx_led_udd_cntx_s {
 165 #ifdef __BIG_ENDIAN_BITFIELD
 166                 uint64_t reserved_6_63:58;
 167                 uint64_t cnt:6;
 168 #else
 169                 uint64_t cnt:6;
 170                 uint64_t reserved_6_63:58;
 171 #endif
 172         } s;
 173 };
 174
 175 union cvmx_led_udd_datx {
 176         uint64_t u64;
 177         struct cvmx_led_udd_datx_s {
 178 #ifdef __BIG_ENDIAN_BITFIELD
 179                 uint64_t reserved_32_63:32;
 180                 uint64_t dat:32;
 181 #else
 182                 uint64_t dat:32;
 183                 uint64_t reserved_32_63:32;
 184 #endif
 185         } s;
 186 };
 187
 188 union cvmx_led_udd_dat_clrx {
 189         uint64_t u64;
 190         struct cvmx_led_udd_dat_clrx_s {
 191 #ifdef __BIG_ENDIAN_BITFIELD
 192                 uint64_t reserved_32_63:32;
 193                 uint64_t clr:32;
 194 #else
 195                 uint64_t clr:32;
 196                 uint64_t reserved_32_63:32;
 197 #endif
 198         } s;
 199 };
 200
 201 union cvmx_led_udd_dat_setx {
 202         uint64_t u64;
 203         struct cvmx_led_udd_dat_setx_s {
 204 #ifdef __BIG_ENDIAN_BITFIELD
 205                 uint64_t reserved_32_63:32;
 206                 uint64_t set:32;
 207 #else
 208                 uint64_t set:32;
 209                 uint64_t reserved_32_63:32;
 210 #endif
 211         } s;
 212 };
 213
 214 #endif