2 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
3 * Copyright (C) 2000 Silicon Graphics, Inc.
4 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
5 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
6 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
7 * Copyright (C) 2003, 2004 Maciej W. Rozycki
9 * SPDX-License-Identifier: GPL-2.0
11 #ifndef _ASM_MIPSREGS_H
12 #define _ASM_MIPSREGS_H
15 * The following macros are especially useful for __asm__
22 #define STR(x) __STR(x)
31 #define _ULCAST_ (unsigned long)
35 * Coprocessor 0 register names
39 #define CP0_ENTRYLO0 $2
40 #define CP0_ENTRYLO1 $3
42 #define CP0_CONTEXT $4
43 #define CP0_PAGEMASK $5
46 #define CP0_HWRENA $7, 0
47 #define CP0_BADVADDR $8
48 #define CP0_BADINSTR $8, 1
50 #define CP0_ENTRYHI $10
51 #define CP0_COMPARE $11
52 #define CP0_STATUS $12
56 #define CP0_EBASE $15, 1
57 #define CP0_CMGCRBASE $15, 3
58 #define CP0_CONFIG $16
59 #define CP0_CONFIG3 $16, 3
60 #define CP0_CONFIG5 $16, 5
61 #define CP0_LLADDR $17
62 #define CP0_WATCHLO $18
63 #define CP0_WATCHHI $19
64 #define CP0_XCONTEXT $20
65 #define CP0_FRAMEMASK $21
66 #define CP0_DIAGNOSTIC $22
69 #define CP0_PERFORMANCE $25
71 #define CP0_CACHEERR $27
74 #define CP0_ERROREPC $30
75 #define CP0_DESAVE $31
78 * R4640/R4650 cp0 register names. These registers are listed
79 * here only for completeness; without MMU these CPUs are not useable
80 * by Linux. A future ELKS port might take make Linux run on them
88 #define CP0_IWATCH $18
89 #define CP0_DWATCH $19
92 * Coprocessor 0 Set 1 register names
94 #define CP0_S1_DERRADDR0 $26
95 #define CP0_S1_DERRADDR1 $27
96 #define CP0_S1_INTCONTROL $20
99 * Coprocessor 0 Set 2 register names
101 #define CP0_S2_SRSCTL $12 /* MIPSR2 */
104 * Coprocessor 0 Set 3 register names
106 #define CP0_S3_SRSMAP $12 /* MIPSR2 */
111 #define CP0_TX39_CACHE $7
114 /* Generic EntryLo bit definitions */
115 #define ENTRYLO_G (_ULCAST_(1) << 0)
116 #define ENTRYLO_V (_ULCAST_(1) << 1)
117 #define ENTRYLO_D (_ULCAST_(1) << 2)
118 #define ENTRYLO_C_SHIFT 3
119 #define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
121 /* R3000 EntryLo bit definitions */
122 #define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
123 #define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
124 #define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
125 #define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
127 /* MIPS32/64 EntryLo bit definitions */
128 #define MIPS_ENTRYLO_PFN_SHIFT 6
129 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
130 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
133 * Values for PageMask register
135 #ifdef CONFIG_CPU_VR41XX
137 /* Why doesn't stupidity hurt ... */
139 #define PM_1K 0x00000000
140 #define PM_4K 0x00001800
141 #define PM_16K 0x00007800
142 #define PM_64K 0x0001f800
143 #define PM_256K 0x0007f800
147 #define PM_4K 0x00000000
148 #define PM_8K 0x00002000
149 #define PM_16K 0x00006000
150 #define PM_32K 0x0000e000
151 #define PM_64K 0x0001e000
152 #define PM_128K 0x0003e000
153 #define PM_256K 0x0007e000
154 #define PM_512K 0x000fe000
155 #define PM_1M 0x001fe000
156 #define PM_2M 0x003fe000
157 #define PM_4M 0x007fe000
158 #define PM_8M 0x00ffe000
159 #define PM_16M 0x01ffe000
160 #define PM_32M 0x03ffe000
161 #define PM_64M 0x07ffe000
162 #define PM_256M 0x1fffe000
163 #define PM_1G 0x7fffe000
168 * Values used for computation of new tlb entries
183 #define PG_RIE (_ULCAST_(1) << 31)
184 #define PG_XIE (_ULCAST_(1) << 30)
185 #define PG_ELPA (_ULCAST_(1) << 29)
186 #define PG_ESP (_ULCAST_(1) << 28)
187 #define PG_IEC (_ULCAST_(1) << 27)
189 /* MIPS32/64 EntryHI bit definitions */
190 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
193 * R4x00 interrupt enable / cause bits
195 #define IE_SW0 (_ULCAST_(1) << 8)
196 #define IE_SW1 (_ULCAST_(1) << 9)
197 #define IE_IRQ0 (_ULCAST_(1) << 10)
198 #define IE_IRQ1 (_ULCAST_(1) << 11)
199 #define IE_IRQ2 (_ULCAST_(1) << 12)
200 #define IE_IRQ3 (_ULCAST_(1) << 13)
201 #define IE_IRQ4 (_ULCAST_(1) << 14)
202 #define IE_IRQ5 (_ULCAST_(1) << 15)
205 * R4x00 interrupt cause bits
207 #define C_SW0 (_ULCAST_(1) << 8)
208 #define C_SW1 (_ULCAST_(1) << 9)
209 #define C_IRQ0 (_ULCAST_(1) << 10)
210 #define C_IRQ1 (_ULCAST_(1) << 11)
211 #define C_IRQ2 (_ULCAST_(1) << 12)
212 #define C_IRQ3 (_ULCAST_(1) << 13)
213 #define C_IRQ4 (_ULCAST_(1) << 14)
214 #define C_IRQ5 (_ULCAST_(1) << 15)
217 * Bitfields in the R4xx0 cp0 status register
219 #define ST0_IE 0x00000001
220 #define ST0_EXL 0x00000002
221 #define ST0_ERL 0x00000004
222 #define ST0_KSU 0x00000018
223 # define KSU_USER 0x00000010
224 # define KSU_SUPERVISOR 0x00000008
225 # define KSU_KERNEL 0x00000000
226 #define ST0_UX 0x00000020
227 #define ST0_SX 0x00000040
228 #define ST0_KX 0x00000080
229 #define ST0_DE 0x00010000
230 #define ST0_CE 0x00020000
233 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
234 * cacheops in userspace. This bit exists only on RM7000 and RM9000
237 #define ST0_CO 0x08000000
240 * Bitfields in the R[23]000 cp0 status register.
242 #define ST0_IEC 0x00000001
243 #define ST0_KUC 0x00000002
244 #define ST0_IEP 0x00000004
245 #define ST0_KUP 0x00000008
246 #define ST0_IEO 0x00000010
247 #define ST0_KUO 0x00000020
248 /* bits 6 & 7 are reserved on R[23]000 */
249 #define ST0_ISC 0x00010000
250 #define ST0_SWC 0x00020000
251 #define ST0_CM 0x00080000
254 * Bits specific to the R4640/R4650
256 #define ST0_UM (_ULCAST_(1) << 4)
257 #define ST0_IL (_ULCAST_(1) << 23)
258 #define ST0_DL (_ULCAST_(1) << 24)
261 * Enable the MIPS MDMX and DSP ASEs
263 #define ST0_MX 0x01000000
266 * Status register bits available in all MIPS CPUs.
268 #define ST0_IM 0x0000ff00
269 #define STATUSB_IP0 8
270 #define STATUSF_IP0 (_ULCAST_(1) << 8)
271 #define STATUSB_IP1 9
272 #define STATUSF_IP1 (_ULCAST_(1) << 9)
273 #define STATUSB_IP2 10
274 #define STATUSF_IP2 (_ULCAST_(1) << 10)
275 #define STATUSB_IP3 11
276 #define STATUSF_IP3 (_ULCAST_(1) << 11)
277 #define STATUSB_IP4 12
278 #define STATUSF_IP4 (_ULCAST_(1) << 12)
279 #define STATUSB_IP5 13
280 #define STATUSF_IP5 (_ULCAST_(1) << 13)
281 #define STATUSB_IP6 14
282 #define STATUSF_IP6 (_ULCAST_(1) << 14)
283 #define STATUSB_IP7 15
284 #define STATUSF_IP7 (_ULCAST_(1) << 15)
285 #define STATUSB_IP8 0
286 #define STATUSF_IP8 (_ULCAST_(1) << 0)
287 #define STATUSB_IP9 1
288 #define STATUSF_IP9 (_ULCAST_(1) << 1)
289 #define STATUSB_IP10 2
290 #define STATUSF_IP10 (_ULCAST_(1) << 2)
291 #define STATUSB_IP11 3
292 #define STATUSF_IP11 (_ULCAST_(1) << 3)
293 #define STATUSB_IP12 4
294 #define STATUSF_IP12 (_ULCAST_(1) << 4)
295 #define STATUSB_IP13 5
296 #define STATUSF_IP13 (_ULCAST_(1) << 5)
297 #define STATUSB_IP14 6
298 #define STATUSF_IP14 (_ULCAST_(1) << 6)
299 #define STATUSB_IP15 7
300 #define STATUSF_IP15 (_ULCAST_(1) << 7)
301 #define ST0_CH 0x00040000
302 #define ST0_NMI 0x00080000
303 #define ST0_SR 0x00100000
304 #define ST0_TS 0x00200000
305 #define ST0_BEV 0x00400000
306 #define ST0_RE 0x02000000
307 #define ST0_FR 0x04000000
308 #define ST0_CU 0xf0000000
309 #define ST0_CU0 0x10000000
310 #define ST0_CU1 0x20000000
311 #define ST0_CU2 0x40000000
312 #define ST0_CU3 0x80000000
313 #define ST0_XX 0x80000000 /* MIPS IV naming */
316 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
318 #define INTCTLB_IPFDC 23
319 #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
320 #define INTCTLB_IPPCI 26
321 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
322 #define INTCTLB_IPTI 29
323 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
326 * Bitfields and bit numbers in the coprocessor 0 cause register.
328 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
330 #define CAUSEB_EXCCODE 2
331 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
333 #define CAUSEF_IP (_ULCAST_(255) << 8)
335 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
337 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
338 #define CAUSEB_IP2 10
339 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
340 #define CAUSEB_IP3 11
341 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
342 #define CAUSEB_IP4 12
343 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
344 #define CAUSEB_IP5 13
345 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
346 #define CAUSEB_IP6 14
347 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
348 #define CAUSEB_IP7 15
349 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
350 #define CAUSEB_FDCI 21
351 #define CAUSEF_FDCI (_ULCAST_(1) << 21)
353 #define CAUSEF_IV (_ULCAST_(1) << 23)
354 #define CAUSEB_PCI 26
355 #define CAUSEF_PCI (_ULCAST_(1) << 26)
357 #define CAUSEF_CE (_ULCAST_(3) << 28)
359 #define CAUSEF_TI (_ULCAST_(1) << 30)
361 #define CAUSEF_BD (_ULCAST_(1) << 31)
364 * Bits in the coprocessor 0 config register.
367 #define CONF_CM_CACHABLE_NO_WA 0
368 #define CONF_CM_CACHABLE_WA 1
369 #define CONF_CM_UNCACHED 2
370 #define CONF_CM_CACHABLE_NONCOHERENT 3
371 #define CONF_CM_CACHABLE_CE 4
372 #define CONF_CM_CACHABLE_COW 5
373 #define CONF_CM_CACHABLE_CUW 6
374 #define CONF_CM_CACHABLE_ACCELERATED 7
375 #define CONF_CM_CMASK 7
376 #define CONF_BE (_ULCAST_(1) << 15)
378 /* Bits common to various processors. */
379 #define CONF_CU (_ULCAST_(1) << 3)
380 #define CONF_DB (_ULCAST_(1) << 4)
381 #define CONF_IB (_ULCAST_(1) << 5)
382 #define CONF_DC (_ULCAST_(7) << 6)
383 #define CONF_IC (_ULCAST_(7) << 9)
384 #define CONF_EB (_ULCAST_(1) << 13)
385 #define CONF_EM (_ULCAST_(1) << 14)
386 #define CONF_SM (_ULCAST_(1) << 16)
387 #define CONF_SC (_ULCAST_(1) << 17)
388 #define CONF_EW (_ULCAST_(3) << 18)
389 #define CONF_EP (_ULCAST_(15) << 24)
390 #define CONF_EC (_ULCAST_(7) << 28)
391 #define CONF_CM (_ULCAST_(1) << 31)
393 /* Bits specific to the R4xx0. */
394 #define R4K_CONF_SW (_ULCAST_(1) << 20)
395 #define R4K_CONF_SS (_ULCAST_(1) << 21)
396 #define R4K_CONF_SB (_ULCAST_(3) << 22)
398 /* Bits specific to the R5000. */
399 #define R5K_CONF_SE (_ULCAST_(1) << 12)
400 #define R5K_CONF_SS (_ULCAST_(3) << 20)
402 /* Bits specific to the RM7000. */
403 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
404 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
405 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
406 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
407 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
408 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
410 /* Bits specific to the R10000. */
411 #define R10K_CONF_DN (_ULCAST_(3) << 3)
412 #define R10K_CONF_CT (_ULCAST_(1) << 5)
413 #define R10K_CONF_PE (_ULCAST_(1) << 6)
414 #define R10K_CONF_PM (_ULCAST_(3) << 7)
415 #define R10K_CONF_EC (_ULCAST_(15) << 9)
416 #define R10K_CONF_SB (_ULCAST_(1) << 13)
417 #define R10K_CONF_SK (_ULCAST_(1) << 14)
418 #define R10K_CONF_SS (_ULCAST_(7) << 16)
419 #define R10K_CONF_SC (_ULCAST_(7) << 19)
420 #define R10K_CONF_DC (_ULCAST_(7) << 26)
421 #define R10K_CONF_IC (_ULCAST_(7) << 29)
423 /* Bits specific to the VR41xx. */
424 #define VR41_CONF_CS (_ULCAST_(1) << 12)
425 #define VR41_CONF_P4K (_ULCAST_(1) << 13)
426 #define VR41_CONF_BP (_ULCAST_(1) << 16)
427 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
428 #define VR41_CONF_AD (_ULCAST_(1) << 23)
430 /* Bits specific to the R30xx. */
431 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
432 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
433 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
434 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
435 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
436 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
437 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
438 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
439 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
441 /* Bits specific to the TX49. */
442 #define TX49_CONF_DC (_ULCAST_(1) << 16)
443 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
444 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
445 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
447 /* Bits specific to the MIPS32/64 PRA. */
448 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
449 #define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
450 #define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
451 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
452 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
453 #define MIPS_CONF_IMPL (_ULCAST_(0x1ff) << 16)
454 #define MIPS_CONF_M (_ULCAST_(1) << 31)
457 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
459 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
460 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
461 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
462 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
463 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
464 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
465 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
466 #define MIPS_CONF1_DA_SHF 7
467 #define MIPS_CONF1_DA_SZ 3
468 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
469 #define MIPS_CONF1_DL_SHF 10
470 #define MIPS_CONF1_DL_SZ 3
471 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
472 #define MIPS_CONF1_DS_SHF 13
473 #define MIPS_CONF1_DS_SZ 3
474 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
475 #define MIPS_CONF1_IA_SHF 16
476 #define MIPS_CONF1_IA_SZ 3
477 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
478 #define MIPS_CONF1_IL_SHF 19
479 #define MIPS_CONF1_IL_SZ 3
480 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
481 #define MIPS_CONF1_IS_SHF 22
482 #define MIPS_CONF1_IS_SZ 3
483 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
484 #define MIPS_CONF1_TLBS_SHIFT (25)
485 #define MIPS_CONF1_TLBS_SIZE (6)
486 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
488 #define MIPS_CONF2_SA (_ULCAST_(15) << 0)
489 #define MIPS_CONF2_SL (_ULCAST_(15) << 4)
490 #define MIPS_CONF2_SS (_ULCAST_(15) << 8)
491 #define MIPS_CONF2_SU (_ULCAST_(15) << 12)
492 #define MIPS_CONF2_TA (_ULCAST_(15) << 16)
493 #define MIPS_CONF2_TL (_ULCAST_(15) << 20)
494 #define MIPS_CONF2_TS (_ULCAST_(15) << 24)
495 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
497 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
498 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
499 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
500 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
501 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
502 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
503 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
504 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
505 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
506 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
507 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
508 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
509 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
510 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
511 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
512 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
513 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
514 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
515 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
516 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
517 #define MIPS_CONF3_PW (_ULCAST_(1) << 24)
518 #define MIPS_CONF3_SC (_ULCAST_(1) << 25)
519 #define MIPS_CONF3_BI (_ULCAST_(1) << 26)
520 #define MIPS_CONF3_BP (_ULCAST_(1) << 27)
521 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
522 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
523 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
525 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
526 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
527 #define MIPS_CONF4_FTLBSETS_SHIFT (0)
528 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
529 #define MIPS_CONF4_FTLBWAYS_SHIFT (4)
530 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
531 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
532 /* bits 10:8 in FTLB-only configurations */
533 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
534 /* bits 12:8 in VTLB-FTLB only configurations */
535 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
536 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
537 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
538 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
539 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
540 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16)
541 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
542 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
543 #define MIPS_CONF4_AE (_ULCAST_(1) << 28)
544 #define MIPS_CONF4_IE (_ULCAST_(3) << 29)
545 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
547 #define MIPS_CONF5_NF (_ULCAST_(1) << 0)
548 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
549 #define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
550 #define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
551 #define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
552 #define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
553 #define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
554 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
555 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
556 #define MIPS_CONF5_CV (_ULCAST_(1) << 29)
557 #define MIPS_CONF5_K (_ULCAST_(1) << 30)
559 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
560 /* proAptiv FTLB on/off bit */
561 #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
562 /* FTLB probability bits */
563 #define MIPS_CONF6_FTLBP_SHIFT (16)
565 #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
567 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
569 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
570 #define MIPS_CONF7_AR (_ULCAST_(1) << 16)
571 /* FTLB probability bits for R6 */
572 #define MIPS_CONF7_FTLBP_SHIFT (18)
574 /* MAAR bit definitions */
575 #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
576 #define MIPS_MAAR_ADDR_SHIFT 12
577 #define MIPS_MAAR_S (_ULCAST_(1) << 1)
578 #define MIPS_MAAR_V (_ULCAST_(1) << 0)
580 /* CMGCRBase bit definitions */
581 #define MIPS_CMGCRB_BASE 11
582 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
585 * Bits in the MIPS32 Memory Segmentation registers.
587 #define MIPS_SEGCFG_PA_SHIFT 9
588 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
589 #define MIPS_SEGCFG_AM_SHIFT 4
590 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
591 #define MIPS_SEGCFG_EU_SHIFT 3
592 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
593 #define MIPS_SEGCFG_C_SHIFT 0
594 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
596 #define MIPS_SEGCFG_UUSK _ULCAST_(7)
597 #define MIPS_SEGCFG_USK _ULCAST_(5)
598 #define MIPS_SEGCFG_MUSUK _ULCAST_(4)
599 #define MIPS_SEGCFG_MUSK _ULCAST_(3)
600 #define MIPS_SEGCFG_MSK _ULCAST_(2)
601 #define MIPS_SEGCFG_MK _ULCAST_(1)
602 #define MIPS_SEGCFG_UK _ULCAST_(0)
604 #define MIPS_PWFIELD_GDI_SHIFT 24
605 #define MIPS_PWFIELD_GDI_MASK 0x3f000000
606 #define MIPS_PWFIELD_UDI_SHIFT 18
607 #define MIPS_PWFIELD_UDI_MASK 0x00fc0000
608 #define MIPS_PWFIELD_MDI_SHIFT 12
609 #define MIPS_PWFIELD_MDI_MASK 0x0003f000
610 #define MIPS_PWFIELD_PTI_SHIFT 6
611 #define MIPS_PWFIELD_PTI_MASK 0x00000fc0
612 #define MIPS_PWFIELD_PTEI_SHIFT 0
613 #define MIPS_PWFIELD_PTEI_MASK 0x0000003f
615 #define MIPS_PWSIZE_GDW_SHIFT 24
616 #define MIPS_PWSIZE_GDW_MASK 0x3f000000
617 #define MIPS_PWSIZE_UDW_SHIFT 18
618 #define MIPS_PWSIZE_UDW_MASK 0x00fc0000
619 #define MIPS_PWSIZE_MDW_SHIFT 12
620 #define MIPS_PWSIZE_MDW_MASK 0x0003f000
621 #define MIPS_PWSIZE_PTW_SHIFT 6
622 #define MIPS_PWSIZE_PTW_MASK 0x00000fc0
623 #define MIPS_PWSIZE_PTEW_SHIFT 0
624 #define MIPS_PWSIZE_PTEW_MASK 0x0000003f
626 #define MIPS_PWCTL_PWEN_SHIFT 31
627 #define MIPS_PWCTL_PWEN_MASK 0x80000000
628 #define MIPS_PWCTL_DPH_SHIFT 7
629 #define MIPS_PWCTL_DPH_MASK 0x00000080
630 #define MIPS_PWCTL_HUGEPG_SHIFT 6
631 #define MIPS_PWCTL_HUGEPG_MASK 0x00000060
632 #define MIPS_PWCTL_PSN_SHIFT 0
633 #define MIPS_PWCTL_PSN_MASK 0x0000003f
635 /* CDMMBase register bit definitions */
636 #define MIPS_CDMMBASE_SIZE_SHIFT 0
637 #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
638 #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
639 #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
640 #define MIPS_CDMMBASE_ADDR_SHIFT 11
641 #define MIPS_CDMMBASE_ADDR_START 15
644 * Bitfields in the TX39 family CP0 Configuration Register 3
646 #define TX39_CONF_ICS_SHIFT 19
647 #define TX39_CONF_ICS_MASK 0x00380000
648 #define TX39_CONF_ICS_1KB 0x00000000
649 #define TX39_CONF_ICS_2KB 0x00080000
650 #define TX39_CONF_ICS_4KB 0x00100000
651 #define TX39_CONF_ICS_8KB 0x00180000
652 #define TX39_CONF_ICS_16KB 0x00200000
654 #define TX39_CONF_DCS_SHIFT 16
655 #define TX39_CONF_DCS_MASK 0x00070000
656 #define TX39_CONF_DCS_1KB 0x00000000
657 #define TX39_CONF_DCS_2KB 0x00010000
658 #define TX39_CONF_DCS_4KB 0x00020000
659 #define TX39_CONF_DCS_8KB 0x00030000
660 #define TX39_CONF_DCS_16KB 0x00040000
662 #define TX39_CONF_CWFON 0x00004000
663 #define TX39_CONF_WBON 0x00002000
664 #define TX39_CONF_RF_SHIFT 10
665 #define TX39_CONF_RF_MASK 0x00000c00
666 #define TX39_CONF_DOZE 0x00000200
667 #define TX39_CONF_HALT 0x00000100
668 #define TX39_CONF_LOCK 0x00000080
669 #define TX39_CONF_ICE 0x00000020
670 #define TX39_CONF_DCE 0x00000010
671 #define TX39_CONF_IRSIZE_SHIFT 2
672 #define TX39_CONF_IRSIZE_MASK 0x0000000c
673 #define TX39_CONF_DRSIZE_SHIFT 0
674 #define TX39_CONF_DRSIZE_MASK 0x00000003
677 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
679 /* Disable Branch Target Address Cache */
680 #define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
681 /* Enable Branch Prediction Global History */
682 #define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
683 /* Disable Branch Return Cache */
684 #define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
687 * Coprocessor 1 (FPU) register names
689 #define CP1_REVISION $0
695 #define CP1_STATUS $31
699 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
701 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
702 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
703 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
704 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
705 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
706 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
707 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
708 #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
709 #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
710 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
713 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
715 #define MIPS_FCCR_CONDX_S 0
716 #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
717 #define MIPS_FCCR_COND0_S 0
718 #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
719 #define MIPS_FCCR_COND1_S 1
720 #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
721 #define MIPS_FCCR_COND2_S 2
722 #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
723 #define MIPS_FCCR_COND3_S 3
724 #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
725 #define MIPS_FCCR_COND4_S 4
726 #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
727 #define MIPS_FCCR_COND5_S 5
728 #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
729 #define MIPS_FCCR_COND6_S 6
730 #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
731 #define MIPS_FCCR_COND7_S 7
732 #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
735 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
737 #define MIPS_FENR_FS_S 2
738 #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
741 * FPU Status Register Values
743 #define FPU_CSR_COND_S 23 /* $fcc0 */
744 #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
746 #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
747 #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
749 #define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
750 #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
751 #define FPU_CSR_COND1_S 25 /* $fcc1 */
752 #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
753 #define FPU_CSR_COND2_S 26 /* $fcc2 */
754 #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
755 #define FPU_CSR_COND3_S 27 /* $fcc3 */
756 #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
757 #define FPU_CSR_COND4_S 28 /* $fcc4 */
758 #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
759 #define FPU_CSR_COND5_S 29 /* $fcc5 */
760 #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
761 #define FPU_CSR_COND6_S 30 /* $fcc6 */
762 #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
763 #define FPU_CSR_COND7_S 31 /* $fcc7 */
764 #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
767 * Bits 22:20 of the FPU Status Register will be read as 0,
768 * and should be written as zero.
770 #define FPU_CSR_RSVD (_ULCAST_(7) << 20)
772 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
773 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
776 * X the exception cause indicator
777 * E the exception enable
778 * S the sticky/flag bit
780 #define FPU_CSR_ALL_X 0x0003f000
781 #define FPU_CSR_UNI_X 0x00020000
782 #define FPU_CSR_INV_X 0x00010000
783 #define FPU_CSR_DIV_X 0x00008000
784 #define FPU_CSR_OVF_X 0x00004000
785 #define FPU_CSR_UDF_X 0x00002000
786 #define FPU_CSR_INE_X 0x00001000
788 #define FPU_CSR_ALL_E 0x00000f80
789 #define FPU_CSR_INV_E 0x00000800
790 #define FPU_CSR_DIV_E 0x00000400
791 #define FPU_CSR_OVF_E 0x00000200
792 #define FPU_CSR_UDF_E 0x00000100
793 #define FPU_CSR_INE_E 0x00000080
795 #define FPU_CSR_ALL_S 0x0000007c
796 #define FPU_CSR_INV_S 0x00000040
797 #define FPU_CSR_DIV_S 0x00000020
798 #define FPU_CSR_OVF_S 0x00000010
799 #define FPU_CSR_UDF_S 0x00000008
800 #define FPU_CSR_INE_S 0x00000004
802 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
803 #define FPU_CSR_RM 0x00000003
804 #define FPU_CSR_RN 0x0 /* nearest */
805 #define FPU_CSR_RZ 0x1 /* towards zero */
806 #define FPU_CSR_RU 0x2 /* towards +Infinity */
807 #define FPU_CSR_RD 0x3 /* towards -Infinity */
813 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
815 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
816 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
817 #define get_isa16_mode(x) ((x) & 0x1)
818 #define msk_isa16_mode(x) ((x) & ~0x1)
819 #define set_isa16_mode(x) do { (x) |= 0x1; } while (0)
821 #define get_isa16_mode(x) 0
822 #define msk_isa16_mode(x) (x)
823 #define set_isa16_mode(x) do { } while (0)
827 * microMIPS instructions can be 16-bit or 32-bit in length. This
828 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
830 static inline int mm_insn_16bit(u16 insn)
832 u16 opcode = (insn >> 10) & 0x7;
834 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
838 * TLB Invalidate Flush
840 static inline void tlbinvf(void)
842 __asm__ __volatile__(
845 ".word 0x42000004\n\t" /* tlbinvf */
851 * Functions to access the R10000 performance counters. These are basically
852 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
853 * performance counter number encoded into bits 1 ... 5 of the instruction.
854 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
855 * disassembler these will look like an access to sel 0 or 1.
857 #define read_r10k_perf_cntr(counter) \
859 unsigned int __res; \
860 __asm__ __volatile__( \
868 #define write_r10k_perf_cntr(counter,val) \
870 __asm__ __volatile__( \
873 : "r" (val), "i" (counter)); \
876 #define read_r10k_perf_event(counter) \
878 unsigned int __res; \
879 __asm__ __volatile__( \
887 #define write_r10k_perf_cntl(counter,val) \
889 __asm__ __volatile__( \
892 : "r" (val), "i" (counter)); \
897 * Macros to access the system control coprocessor
900 #define __read_32bit_c0_register(source, sel) \
901 ({ unsigned int __res; \
903 __asm__ __volatile__( \
904 "mfc0\t%0, " #source "\n\t" \
907 __asm__ __volatile__( \
909 "mfc0\t%0, " #source ", " #sel "\n\t" \
915 #define __read_64bit_c0_register(source, sel) \
916 ({ unsigned long long __res; \
917 if (sizeof(unsigned long) == 4) \
918 __res = __read_64bit_c0_split(source, sel); \
920 __asm__ __volatile__( \
922 "dmfc0\t%0, " #source "\n\t" \
926 __asm__ __volatile__( \
928 "dmfc0\t%0, " #source ", " #sel "\n\t" \
934 #define __write_32bit_c0_register(register, sel, value) \
937 __asm__ __volatile__( \
938 "mtc0\t%z0, " #register "\n\t" \
939 : : "Jr" ((unsigned int)(value))); \
941 __asm__ __volatile__( \
943 "mtc0\t%z0, " #register ", " #sel "\n\t" \
945 : : "Jr" ((unsigned int)(value))); \
948 #define __write_64bit_c0_register(register, sel, value) \
950 if (sizeof(unsigned long) == 4) \
951 __write_64bit_c0_split(register, sel, value); \
953 __asm__ __volatile__( \
955 "dmtc0\t%z0, " #register "\n\t" \
959 __asm__ __volatile__( \
961 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
966 #define __read_ulong_c0_register(reg, sel) \
967 ((sizeof(unsigned long) == 4) ? \
968 (unsigned long) __read_32bit_c0_register(reg, sel) : \
969 (unsigned long) __read_64bit_c0_register(reg, sel))
971 #define __write_ulong_c0_register(reg, sel, val) \
973 if (sizeof(unsigned long) == 4) \
974 __write_32bit_c0_register(reg, sel, val); \
976 __write_64bit_c0_register(reg, sel, val); \
980 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
982 #define __read_32bit_c0_ctrl_register(source) \
983 ({ unsigned int __res; \
984 __asm__ __volatile__( \
985 "cfc0\t%0, " #source "\n\t" \
990 #define __write_32bit_c0_ctrl_register(register, value) \
992 __asm__ __volatile__( \
993 "ctc0\t%z0, " #register "\n\t" \
994 : : "Jr" ((unsigned int)(value))); \
998 * These versions are only needed for systems with more than 38 bits of
999 * physical address space running the 32-bit kernel. That's none atm :-)
1001 #define __read_64bit_c0_split(source, sel) \
1003 unsigned long long __val; \
1004 unsigned long __flags; \
1006 local_irq_save(__flags); \
1008 __asm__ __volatile__( \
1009 ".set\tmips64\n\t" \
1010 "dmfc0\t%M0, " #source "\n\t" \
1011 "dsll\t%L0, %M0, 32\n\t" \
1012 "dsra\t%M0, %M0, 32\n\t" \
1013 "dsra\t%L0, %L0, 32\n\t" \
1017 __asm__ __volatile__( \
1018 ".set\tmips64\n\t" \
1019 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
1020 "dsll\t%L0, %M0, 32\n\t" \
1021 "dsra\t%M0, %M0, 32\n\t" \
1022 "dsra\t%L0, %L0, 32\n\t" \
1025 local_irq_restore(__flags); \
1030 #define __write_64bit_c0_split(source, sel, val) \
1032 unsigned long __flags; \
1034 local_irq_save(__flags); \
1036 __asm__ __volatile__( \
1037 ".set\tmips64\n\t" \
1038 "dsll\t%L0, %L0, 32\n\t" \
1039 "dsrl\t%L0, %L0, 32\n\t" \
1040 "dsll\t%M0, %M0, 32\n\t" \
1041 "or\t%L0, %L0, %M0\n\t" \
1042 "dmtc0\t%L0, " #source "\n\t" \
1046 __asm__ __volatile__( \
1047 ".set\tmips64\n\t" \
1048 "dsll\t%L0, %L0, 32\n\t" \
1049 "dsrl\t%L0, %L0, 32\n\t" \
1050 "dsll\t%M0, %M0, 32\n\t" \
1051 "or\t%L0, %L0, %M0\n\t" \
1052 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1055 local_irq_restore(__flags); \
1058 #define __readx_32bit_c0_register(source) \
1060 unsigned int __res; \
1062 __asm__ __volatile__( \
1065 " .set mips32r2 \n" \
1067 " # mfhc0 $1, %1 \n" \
1068 " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \
1076 #define __writex_32bit_c0_register(register, value) \
1078 __asm__ __volatile__( \
1081 " .set mips32r2 \n" \
1083 " # mthc0 $1, %1 \n" \
1085 " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \
1088 : "r" (value), "i" (register)); \
1091 #define read_c0_index() __read_32bit_c0_register($0, 0)
1092 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1094 #define read_c0_random() __read_32bit_c0_register($1, 0)
1095 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1097 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1098 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1100 #define readx_c0_entrylo0() __readx_32bit_c0_register(2)
1101 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1103 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1104 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1106 #define readx_c0_entrylo1() __readx_32bit_c0_register(3)
1107 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1109 #define read_c0_conf() __read_32bit_c0_register($3, 0)
1110 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1112 #define read_c0_context() __read_ulong_c0_register($4, 0)
1113 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1115 #define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1116 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1118 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1119 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1121 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1122 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1124 #define read_c0_wired() __read_32bit_c0_register($6, 0)
1125 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1127 #define read_c0_info() __read_32bit_c0_register($7, 0)
1129 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1130 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1132 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1133 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1135 #define read_c0_count() __read_32bit_c0_register($9, 0)
1136 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1138 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
1139 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1141 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
1142 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1144 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1145 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1147 #define read_c0_compare() __read_32bit_c0_register($11, 0)
1148 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1150 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
1151 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1153 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
1154 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1156 #define read_c0_status() __read_32bit_c0_register($12, 0)
1158 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1160 #define read_c0_cause() __read_32bit_c0_register($13, 0)
1161 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1163 #define read_c0_epc() __read_ulong_c0_register($14, 0)
1164 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1166 #define read_c0_prid() __read_32bit_c0_register($15, 0)
1168 #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1170 #define read_c0_config() __read_32bit_c0_register($16, 0)
1171 #define read_c0_config1() __read_32bit_c0_register($16, 1)
1172 #define read_c0_config2() __read_32bit_c0_register($16, 2)
1173 #define read_c0_config3() __read_32bit_c0_register($16, 3)
1174 #define read_c0_config4() __read_32bit_c0_register($16, 4)
1175 #define read_c0_config5() __read_32bit_c0_register($16, 5)
1176 #define read_c0_config6() __read_32bit_c0_register($16, 6)
1177 #define read_c0_config7() __read_32bit_c0_register($16, 7)
1178 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1179 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1180 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1181 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1182 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1183 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1184 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1185 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1187 #define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1188 #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1189 #define read_c0_maar() __read_ulong_c0_register($17, 1)
1190 #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1191 #define read_c0_maari() __read_32bit_c0_register($17, 2)
1192 #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1195 * The WatchLo register. There may be up to 8 of them.
1197 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1198 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1199 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1200 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1201 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1202 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1203 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1204 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1205 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1206 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1207 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1208 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1209 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1210 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1211 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1212 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1215 * The WatchHi register. There may be up to 8 of them.
1217 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1218 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1219 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1220 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1221 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1222 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1223 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1224 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1226 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1227 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1228 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1229 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1230 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1231 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1232 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1233 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1235 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1236 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1238 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1239 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1241 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
1242 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1244 #define read_c0_diag() __read_32bit_c0_register($22, 0)
1245 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1247 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1248 #define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1249 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1251 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
1252 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1254 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
1255 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1257 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
1258 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1260 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
1261 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1263 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
1264 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1266 #define read_c0_debug() __read_32bit_c0_register($23, 0)
1267 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1269 #define read_c0_depc() __read_ulong_c0_register($24, 0)
1270 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1273 * MIPS32 / MIPS64 performance counters
1275 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1276 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1277 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1278 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1279 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1280 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1281 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1282 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1283 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1284 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1285 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1286 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1287 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1288 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1289 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1290 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1291 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1292 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1293 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1294 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1295 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1296 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1297 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1298 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1300 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
1301 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1303 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1304 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1306 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1308 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1309 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1311 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
1312 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1314 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1315 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1317 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1318 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1320 #define read_c0_staglo() __read_32bit_c0_register($28, 4)
1321 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1323 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
1324 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1326 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1327 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1330 #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1331 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1333 #define read_c0_intctl() __read_32bit_c0_register($12, 1)
1334 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1336 #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1337 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1339 #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1340 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1342 #define read_c0_ebase() __read_32bit_c0_register($15, 1)
1343 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1345 #define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1346 #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1349 #define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1350 #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1352 #define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1353 #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1355 #define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1356 #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1358 /* Hardware Page Table Walker */
1359 #define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1360 #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1362 #define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1363 #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1365 #define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1366 #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1368 #define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1369 #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1371 /* Cavium OCTEON (cnMIPS) */
1372 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1373 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1375 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1376 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1378 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1379 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1381 * The cacheerr registers are not standardized. On OCTEON, they are
1384 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1385 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1387 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1388 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1391 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1392 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1394 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1395 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1397 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1398 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1401 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1402 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1404 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1405 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1407 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1408 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1410 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1411 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1413 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1414 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1417 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1418 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1420 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1421 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1423 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1424 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1426 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1427 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1429 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1430 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1432 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1433 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1436 * Macros to access the floating point coprocessor control registers
1438 #define _read_32bit_cp1_register(source, gas_hardfloat) \
1440 unsigned int __res; \
1442 __asm__ __volatile__( \
1444 " .set reorder \n" \
1445 " # gas fails to assemble cfc1 for some archs, \n" \
1446 " # like Octeon. \n" \
1448 " "STR(gas_hardfloat)" \n" \
1449 " cfc1 %0,"STR(source)" \n" \
1455 #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
1457 __asm__ __volatile__( \
1459 " .set reorder \n" \
1460 " "STR(gas_hardfloat)" \n" \
1461 " ctc1 %0,"STR(dest)" \n" \
1466 #ifdef GAS_HAS_SET_HARDFLOAT
1467 #define read_32bit_cp1_register(source) \
1468 _read_32bit_cp1_register(source, .set hardfloat)
1469 #define write_32bit_cp1_register(dest, val) \
1470 _write_32bit_cp1_register(dest, val, .set hardfloat)
1472 #define read_32bit_cp1_register(source) \
1473 _read_32bit_cp1_register(source, )
1474 #define write_32bit_cp1_register(dest, val) \
1475 _write_32bit_cp1_register(dest, val, )
1479 #define rddsp(mask) \
1481 unsigned int __dspctl; \
1483 __asm__ __volatile__( \
1486 " rddsp %0, %x1 \n" \
1493 #define wrdsp(val, mask) \
1495 __asm__ __volatile__( \
1498 " wrdsp %0, %x1 \n" \
1501 : "r" (val), "i" (mask)); \
1510 " mflo %0, $ac0 \n" \
1522 " mflo %0, $ac1 \n" \
1534 " mflo %0, $ac2 \n" \
1546 " mflo %0, $ac3 \n" \
1558 " mfhi %0, $ac0 \n" \
1570 " mfhi %0, $ac1 \n" \
1582 " mfhi %0, $ac2 \n" \
1594 " mfhi %0, $ac3 \n" \
1606 " mtlo %0, $ac0 \n" \
1617 " mtlo %0, $ac1 \n" \
1628 " mtlo %0, $ac2 \n" \
1639 " mtlo %0, $ac3 \n" \
1650 " mthi %0, $ac0 \n" \
1661 " mthi %0, $ac1 \n" \
1672 " mthi %0, $ac2 \n" \
1683 " mthi %0, $ac3 \n" \
1691 #ifdef CONFIG_CPU_MICROMIPS
1692 #define rddsp(mask) \
1694 unsigned int __res; \
1696 __asm__ __volatile__( \
1699 " # rddsp $1, %x1 \n" \
1700 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
1701 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
1709 #define wrdsp(val, mask) \
1711 __asm__ __volatile__( \
1715 " # wrdsp $1, %x1 \n" \
1716 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
1717 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
1720 : "r" (val), "i" (mask)); \
1723 #define _umips_dsp_mfxxx(ins) \
1725 unsigned long __treg; \
1727 __asm__ __volatile__( \
1730 " .hword 0x0001 \n" \
1739 #define _umips_dsp_mtxxx(val, ins) \
1741 __asm__ __volatile__( \
1745 " .hword 0x0001 \n" \
1749 : "r" (val), "i" (ins)); \
1752 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1753 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1755 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1756 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1758 #define mflo0() _umips_dsp_mflo(0)
1759 #define mflo1() _umips_dsp_mflo(1)
1760 #define mflo2() _umips_dsp_mflo(2)
1761 #define mflo3() _umips_dsp_mflo(3)
1763 #define mfhi0() _umips_dsp_mfhi(0)
1764 #define mfhi1() _umips_dsp_mfhi(1)
1765 #define mfhi2() _umips_dsp_mfhi(2)
1766 #define mfhi3() _umips_dsp_mfhi(3)
1768 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1769 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1770 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1771 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1773 #define mthi0(x) _umips_dsp_mthi(x, 0)
1774 #define mthi1(x) _umips_dsp_mthi(x, 1)
1775 #define mthi2(x) _umips_dsp_mthi(x, 2)
1776 #define mthi3(x) _umips_dsp_mthi(x, 3)
1778 #else /* !CONFIG_CPU_MICROMIPS */
1779 #define rddsp(mask) \
1781 unsigned int __res; \
1783 __asm__ __volatile__( \
1786 " # rddsp $1, %x1 \n" \
1787 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1795 #define wrdsp(val, mask) \
1797 __asm__ __volatile__( \
1801 " # wrdsp $1, %x1 \n" \
1802 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1805 : "r" (val), "i" (mask)); \
1808 #define _dsp_mfxxx(ins) \
1810 unsigned long __treg; \
1812 __asm__ __volatile__( \
1815 " .word (0x00000810 | %1) \n" \
1823 #define _dsp_mtxxx(val, ins) \
1825 __asm__ __volatile__( \
1829 " .word (0x00200011 | %1) \n" \
1832 : "r" (val), "i" (ins)); \
1835 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1836 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1838 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1839 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1841 #define mflo0() _dsp_mflo(0)
1842 #define mflo1() _dsp_mflo(1)
1843 #define mflo2() _dsp_mflo(2)
1844 #define mflo3() _dsp_mflo(3)
1846 #define mfhi0() _dsp_mfhi(0)
1847 #define mfhi1() _dsp_mfhi(1)
1848 #define mfhi2() _dsp_mfhi(2)
1849 #define mfhi3() _dsp_mfhi(3)
1851 #define mtlo0(x) _dsp_mtlo(x, 0)
1852 #define mtlo1(x) _dsp_mtlo(x, 1)
1853 #define mtlo2(x) _dsp_mtlo(x, 2)
1854 #define mtlo3(x) _dsp_mtlo(x, 3)
1856 #define mthi0(x) _dsp_mthi(x, 0)
1857 #define mthi1(x) _dsp_mthi(x, 1)
1858 #define mthi2(x) _dsp_mthi(x, 2)
1859 #define mthi3(x) _dsp_mthi(x, 3)
1861 #endif /* CONFIG_CPU_MICROMIPS */
1867 * It is responsibility of the caller to take care of any TLB hazards.
1869 static inline void tlb_probe(void)
1871 __asm__ __volatile__(
1872 ".set noreorder\n\t"
1877 static inline void tlb_read(void)
1879 #if MIPS34K_MISSED_ITLB_WAR
1882 __asm__ __volatile__(
1884 " .set noreorder \n"
1887 " .word 0x41610001 # dvpe $1 \n"
1893 instruction_hazard();
1896 __asm__ __volatile__(
1897 ".set noreorder\n\t"
1901 #if MIPS34K_MISSED_ITLB_WAR
1902 if ((res & _ULCAST_(1)))
1903 __asm__ __volatile__(
1905 " .set noreorder \n"
1908 " .word 0x41600021 # evpe \n"
1914 static inline void tlb_write_indexed(void)
1916 __asm__ __volatile__(
1917 ".set noreorder\n\t"
1922 static inline void tlb_write_random(void)
1924 __asm__ __volatile__(
1925 ".set noreorder\n\t"
1931 * Manipulate bits in a c0 register.
1933 #define __BUILD_SET_C0(name) \
1934 static inline unsigned int \
1935 set_c0_##name(unsigned int set) \
1937 unsigned int res, new; \
1939 res = read_c0_##name(); \
1941 write_c0_##name(new); \
1946 static inline unsigned int \
1947 clear_c0_##name(unsigned int clear) \
1949 unsigned int res, new; \
1951 res = read_c0_##name(); \
1952 new = res & ~clear; \
1953 write_c0_##name(new); \
1958 static inline unsigned int \
1959 change_c0_##name(unsigned int change, unsigned int val) \
1961 unsigned int res, new; \
1963 res = read_c0_##name(); \
1964 new = res & ~change; \
1965 new |= (val & change); \
1966 write_c0_##name(new); \
1971 __BUILD_SET_C0(status)
1972 __BUILD_SET_C0(cause)
1973 __BUILD_SET_C0(config)
1974 __BUILD_SET_C0(config5)
1975 __BUILD_SET_C0(intcontrol)
1976 __BUILD_SET_C0(intctl)
1977 __BUILD_SET_C0(srsmap)
1978 __BUILD_SET_C0(pagegrain)
1979 __BUILD_SET_C0(brcm_config_0)
1980 __BUILD_SET_C0(brcm_bus_pll)
1981 __BUILD_SET_C0(brcm_reset)
1982 __BUILD_SET_C0(brcm_cmt_intr)
1983 __BUILD_SET_C0(brcm_cmt_ctrl)
1984 __BUILD_SET_C0(brcm_config)
1985 __BUILD_SET_C0(brcm_mode)
1988 * Return low 10 bits of ebase.
1989 * Note that under KVM (MIPSVZ) this returns vcpu id.
1991 static inline unsigned int get_ebase_cpunum(void)
1993 return read_c0_ebase() & 0x3ff;
1996 #endif /* !__ASSEMBLY__ */
1998 #endif /* _ASM_MIPSREGS_H */