arch/mips/include/asm/mipsregs.h

   1 /*
   2  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   3  * Copyright (C) 2000 Silicon Graphics, Inc.
   4  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   5  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
   6  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
   7  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0
  10  */
  11 #ifndef _ASM_MIPSREGS_H
  12 #define _ASM_MIPSREGS_H
  13
  14 /*
  15  * The following macros are especially useful for __asm__
  16  * inline assembler.
  17  */
  18 #ifndef __STR
  19 #define __STR(x) #x
  20 #endif
  21 #ifndef STR
  22 #define STR(x) __STR(x)
  23 #endif
  24
  25 /*
  26  *  Configure language
  27  */
  28 #ifdef __ASSEMBLY__
  29 #define _ULCAST_
  30 #else
  31 #define _ULCAST_ (unsigned long)
  32 #endif
  33
  34 /*
  35  * Coprocessor 0 register names
  36  */
  37 #define CP0_INDEX $0
  38 #define CP0_RANDOM $1
  39 #define CP0_ENTRYLO0 $2
  40 #define CP0_ENTRYLO1 $3
  41 #define CP0_CONF $3
  42 #define CP0_GLOBALNUMBER $3, 1
  43 #define CP0_CONTEXT $4
  44 #define CP0_PAGEMASK $5
  45 #define CP0_WIRED $6
  46 #define CP0_INFO $7
  47 #define CP0_HWRENA $7, 0
  48 #define CP0_BADVADDR $8
  49 #define CP0_BADINSTR $8, 1
  50 #define CP0_COUNT $9
  51 #define CP0_ENTRYHI $10
  52 #define CP0_COMPARE $11
  53 #define CP0_STATUS $12
  54 #define CP0_CAUSE $13
  55 #define CP0_EPC $14
  56 #define CP0_PRID $15
  57 #define CP0_EBASE $15, 1
  58 #define CP0_CMGCRBASE $15, 3
  59 #define CP0_CONFIG $16
  60 #define CP0_CONFIG3 $16, 3
  61 #define CP0_CONFIG5 $16, 5
  62 #define CP0_LLADDR $17
  63 #define CP0_WATCHLO $18
  64 #define CP0_WATCHHI $19
  65 #define CP0_XCONTEXT $20
  66 #define CP0_FRAMEMASK $21
  67 #define CP0_DIAGNOSTIC $22
  68 #define CP0_DEBUG $23
  69 #define CP0_DEPC $24
  70 #define CP0_PERFORMANCE $25
  71 #define CP0_ECC $26
  72 #define CP0_CACHEERR $27
  73 #define CP0_TAGLO $28
  74 #define CP0_TAGHI $29
  75 #define CP0_ERROREPC $30
  76 #define CP0_DESAVE $31
  77
  78 /*
  79  * R4640/R4650 cp0 register names.  These registers are listed
  80  * here only for completeness; without MMU these CPUs are not useable
  81  * by Linux.  A future ELKS port might take make Linux run on them
  82  * though ...
  83  */
  84 #define CP0_IBASE $0
  85 #define CP0_IBOUND $1
  86 #define CP0_DBASE $2
  87 #define CP0_DBOUND $3
  88 #define CP0_CALG $17
  89 #define CP0_IWATCH $18
  90 #define CP0_DWATCH $19
  91
  92 /*
  93  * Coprocessor 0 Set 1 register names
  94  */
  95 #define CP0_S1_DERRADDR0  $26
  96 #define CP0_S1_DERRADDR1  $27
  97 #define CP0_S1_INTCONTROL $20
  98
  99 /*
 100  * Coprocessor 0 Set 2 register names
 101  */
 102 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 103
 104 /*
 105  * Coprocessor 0 Set 3 register names
 106  */
 107 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 108
 109 /*
 110  *  TX39 Series
 111  */
 112 #define CP0_TX39_CACHE  $7
 113
 114
 115 /* Generic EntryLo bit definitions */
 116 #define ENTRYLO_G               (_ULCAST_(1) << 0)
 117 #define ENTRYLO_V               (_ULCAST_(1) << 1)
 118 #define ENTRYLO_D               (_ULCAST_(1) << 2)
 119 #define ENTRYLO_C_SHIFT         3
 120 #define ENTRYLO_C               (_ULCAST_(7) << ENTRYLO_C_SHIFT)
 121
 122 /* R3000 EntryLo bit definitions */
 123 #define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
 124 #define R3K_ENTRYLO_V           (_ULCAST_(1) << 9)
 125 #define R3K_ENTRYLO_D           (_ULCAST_(1) << 10)
 126 #define R3K_ENTRYLO_N           (_ULCAST_(1) << 11)
 127
 128 /* MIPS32/64 EntryLo bit definitions */
 129 #define MIPS_ENTRYLO_PFN_SHIFT  6
 130 #define MIPS_ENTRYLO_XI         (_ULCAST_(1) << (BITS_PER_LONG - 2))
 131 #define MIPS_ENTRYLO_RI         (_ULCAST_(1) << (BITS_PER_LONG - 1))
 132
 133 /*
 134  * Values for PageMask register
 135  */
 136 #ifdef CONFIG_CPU_VR41XX
 137
 138 /* Why doesn't stupidity hurt ... */
 139
 140 #define PM_1K           0x00000000
 141 #define PM_4K           0x00001800
 142 #define PM_16K          0x00007800
 143 #define PM_64K          0x0001f800
 144 #define PM_256K         0x0007f800
 145
 146 #else
 147
 148 #define PM_4K           0x00000000
 149 #define PM_8K           0x00002000
 150 #define PM_16K          0x00006000
 151 #define PM_32K          0x0000e000
 152 #define PM_64K          0x0001e000
 153 #define PM_128K         0x0003e000
 154 #define PM_256K         0x0007e000
 155 #define PM_512K         0x000fe000
 156 #define PM_1M           0x001fe000
 157 #define PM_2M           0x003fe000
 158 #define PM_4M           0x007fe000
 159 #define PM_8M           0x00ffe000
 160 #define PM_16M          0x01ffe000
 161 #define PM_32M          0x03ffe000
 162 #define PM_64M          0x07ffe000
 163 #define PM_256M         0x1fffe000
 164 #define PM_1G           0x7fffe000
 165
 166 #endif
 167
 168 /*
 169  * Values used for computation of new tlb entries
 170  */
 171 #define PL_4K           12
 172 #define PL_16K          14
 173 #define PL_64K          16
 174 #define PL_256K         18
 175 #define PL_1M           20
 176 #define PL_4M           22
 177 #define PL_16M          24
 178 #define PL_64M          26
 179 #define PL_256M         28
 180
 181 /*
 182  * PageGrain bits
 183  */
 184 #define PG_RIE          (_ULCAST_(1) <<  31)
 185 #define PG_XIE          (_ULCAST_(1) <<  30)
 186 #define PG_ELPA         (_ULCAST_(1) <<  29)
 187 #define PG_ESP          (_ULCAST_(1) <<  28)
 188 #define PG_IEC          (_ULCAST_(1) <<  27)
 189
 190 /* MIPS32/64 EntryHI bit definitions */
 191 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 192
 193 /*
 194  * R4x00 interrupt enable / cause bits
 195  */
 196 #define IE_SW0          (_ULCAST_(1) <<  8)
 197 #define IE_SW1          (_ULCAST_(1) <<  9)
 198 #define IE_IRQ0         (_ULCAST_(1) << 10)
 199 #define IE_IRQ1         (_ULCAST_(1) << 11)
 200 #define IE_IRQ2         (_ULCAST_(1) << 12)
 201 #define IE_IRQ3         (_ULCAST_(1) << 13)
 202 #define IE_IRQ4         (_ULCAST_(1) << 14)
 203 #define IE_IRQ5         (_ULCAST_(1) << 15)
 204
 205 /*
 206  * R4x00 interrupt cause bits
 207  */
 208 #define C_SW0           (_ULCAST_(1) <<  8)
 209 #define C_SW1           (_ULCAST_(1) <<  9)
 210 #define C_IRQ0          (_ULCAST_(1) << 10)
 211 #define C_IRQ1          (_ULCAST_(1) << 11)
 212 #define C_IRQ2          (_ULCAST_(1) << 12)
 213 #define C_IRQ3          (_ULCAST_(1) << 13)
 214 #define C_IRQ4          (_ULCAST_(1) << 14)
 215 #define C_IRQ5          (_ULCAST_(1) << 15)
 216
 217 /*
 218  * Bitfields in the R4xx0 cp0 status register
 219  */
 220 #define ST0_IE                  0x00000001
 221 #define ST0_EXL                 0x00000002
 222 #define ST0_ERL                 0x00000004
 223 #define ST0_KSU                 0x00000018
 224 #  define KSU_USER              0x00000010
 225 #  define KSU_SUPERVISOR        0x00000008
 226 #  define KSU_KERNEL            0x00000000
 227 #define ST0_UX                  0x00000020
 228 #define ST0_SX                  0x00000040
 229 #define ST0_KX                  0x00000080
 230 #define ST0_DE                  0x00010000
 231 #define ST0_CE                  0x00020000
 232
 233 /*
 234  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 235  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 236  * processors.
 237  */
 238 #define ST0_CO                  0x08000000
 239
 240 /*
 241  * Bitfields in the R[23]000 cp0 status register.
 242  */
 243 #define ST0_IEC                 0x00000001
 244 #define ST0_KUC                 0x00000002
 245 #define ST0_IEP                 0x00000004
 246 #define ST0_KUP                 0x00000008
 247 #define ST0_IEO                 0x00000010
 248 #define ST0_KUO                 0x00000020
 249 /* bits 6 & 7 are reserved on R[23]000 */
 250 #define ST0_ISC                 0x00010000
 251 #define ST0_SWC                 0x00020000
 252 #define ST0_CM                  0x00080000
 253
 254 /*
 255  * Bits specific to the R4640/R4650
 256  */
 257 #define ST0_UM                  (_ULCAST_(1) <<  4)
 258 #define ST0_IL                  (_ULCAST_(1) << 23)
 259 #define ST0_DL                  (_ULCAST_(1) << 24)
 260
 261 /*
 262  * Enable the MIPS MDMX and DSP ASEs
 263  */
 264 #define ST0_MX                  0x01000000
 265
 266 /*
 267  * Status register bits available in all MIPS CPUs.
 268  */
 269 #define ST0_IM                  0x0000ff00
 270 #define  STATUSB_IP0            8
 271 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 272 #define  STATUSB_IP1            9
 273 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 274 #define  STATUSB_IP2            10
 275 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 276 #define  STATUSB_IP3            11
 277 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 278 #define  STATUSB_IP4            12
 279 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 280 #define  STATUSB_IP5            13
 281 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 282 #define  STATUSB_IP6            14
 283 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 284 #define  STATUSB_IP7            15
 285 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 286 #define  STATUSB_IP8            0
 287 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 288 #define  STATUSB_IP9            1
 289 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 290 #define  STATUSB_IP10           2
 291 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 292 #define  STATUSB_IP11           3
 293 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 294 #define  STATUSB_IP12           4
 295 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 296 #define  STATUSB_IP13           5
 297 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 298 #define  STATUSB_IP14           6
 299 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 300 #define  STATUSB_IP15           7
 301 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 302 #define ST0_IMPL                (_ULCAST_(3) <<  16)
 303 #define ST0_CH                  0x00040000
 304 #define ST0_NMI                 0x00080000
 305 #define ST0_SR                  0x00100000
 306 #define ST0_TS                  0x00200000
 307 #define ST0_BEV                 0x00400000
 308 #define ST0_RE                  0x02000000
 309 #define ST0_FR                  0x04000000
 310 #define ST0_CU                  0xf0000000
 311 #define ST0_CU0                 0x10000000
 312 #define ST0_CU1                 0x20000000
 313 #define ST0_CU2                 0x40000000
 314 #define ST0_CU3                 0x80000000
 315 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 316
 317 /*
 318  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 319  */
 320 #define INTCTLB_IPFDC           23
 321 #define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
 322 #define INTCTLB_IPPCI           26
 323 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 324 #define INTCTLB_IPTI            29
 325 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 326
 327 /*
 328  * Bitfields and bit numbers in the coprocessor 0 cause register.
 329  *
 330  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 331  */
 332 #define CAUSEB_EXCCODE          2
 333 #define CAUSEF_EXCCODE          (_ULCAST_(31)  <<  2)
 334 #define CAUSEB_IP               8
 335 #define CAUSEF_IP               (_ULCAST_(255) <<  8)
 336 #define  CAUSEB_IP0             8
 337 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 338 #define  CAUSEB_IP1             9
 339 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 340 #define  CAUSEB_IP2             10
 341 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 342 #define  CAUSEB_IP3             11
 343 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 344 #define  CAUSEB_IP4             12
 345 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 346 #define  CAUSEB_IP5             13
 347 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 348 #define  CAUSEB_IP6             14
 349 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 350 #define  CAUSEB_IP7             15
 351 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 352 #define CAUSEB_FDCI             21
 353 #define CAUSEF_FDCI             (_ULCAST_(1)   << 21)
 354 #define CAUSEB_IV               23
 355 #define CAUSEF_IV               (_ULCAST_(1)   << 23)
 356 #define CAUSEB_PCI              26
 357 #define CAUSEF_PCI              (_ULCAST_(1)   << 26)
 358 #define CAUSEB_CE               28
 359 #define CAUSEF_CE               (_ULCAST_(3)   << 28)
 360 #define CAUSEB_TI               30
 361 #define CAUSEF_TI               (_ULCAST_(1)   << 30)
 362 #define CAUSEB_BD               31
 363 #define CAUSEF_BD               (_ULCAST_(1)   << 31)
 364
 365 /*
 366  * Bits in the coprocessor 0 EBase register.
 367  */
 368 #define EBASE_CPUNUM            0x3ff
 369
 370 /*
 371  * Bits in the coprocessor 0 config register.
 372  */
 373 /* Generic bits.  */
 374 #define CONF_CM_CACHABLE_NO_WA          0
 375 #define CONF_CM_CACHABLE_WA             1
 376 #define CONF_CM_UNCACHED                2
 377 #define CONF_CM_CACHABLE_NONCOHERENT    3
 378 #define CONF_CM_CACHABLE_CE             4
 379 #define CONF_CM_CACHABLE_COW            5
 380 #define CONF_CM_CACHABLE_CUW            6
 381 #define CONF_CM_CACHABLE_ACCELERATED    7
 382 #define CONF_CM_CMASK                   7
 383 #define CONF_BE                 (_ULCAST_(1) << 15)
 384
 385 /* Bits common to various processors.  */
 386 #define CONF_CU                 (_ULCAST_(1) <<  3)
 387 #define CONF_DB                 (_ULCAST_(1) <<  4)
 388 #define CONF_IB                 (_ULCAST_(1) <<  5)
 389 #define CONF_DC                 (_ULCAST_(7) <<  6)
 390 #define CONF_IC                 (_ULCAST_(7) <<  9)
 391 #define CONF_EB                 (_ULCAST_(1) << 13)
 392 #define CONF_EM                 (_ULCAST_(1) << 14)
 393 #define CONF_SM                 (_ULCAST_(1) << 16)
 394 #define CONF_SC                 (_ULCAST_(1) << 17)
 395 #define CONF_EW                 (_ULCAST_(3) << 18)
 396 #define CONF_EP                 (_ULCAST_(15) << 24)
 397 #define CONF_EC                 (_ULCAST_(7) << 28)
 398 #define CONF_CM                 (_ULCAST_(1) << 31)
 399
 400 /* Bits specific to the R4xx0.  */
 401 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 402 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 403 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 404
 405 /* Bits specific to the R5000.  */
 406 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 407 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 408
 409 /* Bits specific to the RM7000.  */
 410 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 411 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 412 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 413 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 414 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 415 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 416
 417 /* Bits specific to the R10000.  */
 418 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 419 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 420 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 421 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 422 #define R10K_CONF_EC            (_ULCAST_(15) << 9)
 423 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 424 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 425 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 426 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 427 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 428 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 429
 430 /* Bits specific to the VR41xx.  */
 431 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 432 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 433 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 434 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 435 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 436
 437 /* Bits specific to the R30xx.  */
 438 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 439 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 440 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 441 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 442 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 443 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 444 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 445 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 446 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 447
 448 /* Bits specific to the TX49.  */
 449 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 450 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 451 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 452 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 453
 454 /* Bits specific to the MIPS32/64 PRA.  */
 455 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 456 #define MIPS_CONF_MT_TLB        (_ULCAST_(1) <<  7)
 457 #define MIPS_CONF_MT_FTLB       (_ULCAST_(4) <<  7)
 458 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 459 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 460 #define MIPS_CONF_IMPL          (_ULCAST_(0x1ff) << 16)
 461 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 462
 463 /*
 464  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 465  */
 466 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 467 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 468 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 469 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 470 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 471 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 472 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 473 #define MIPS_CONF1_DA_SHF       7
 474 #define MIPS_CONF1_DA_SZ        3
 475 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 476 #define MIPS_CONF1_DL_SHF       10
 477 #define MIPS_CONF1_DL_SZ        3
 478 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 479 #define MIPS_CONF1_DS_SHF       13
 480 #define MIPS_CONF1_DS_SZ        3
 481 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 482 #define MIPS_CONF1_IA_SHF       16
 483 #define MIPS_CONF1_IA_SZ        3
 484 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 485 #define MIPS_CONF1_IL_SHF       19
 486 #define MIPS_CONF1_IL_SZ        3
 487 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 488 #define MIPS_CONF1_IS_SHF       22
 489 #define MIPS_CONF1_IS_SZ        3
 490 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 491 #define MIPS_CONF1_TLBS_SHIFT   (25)
 492 #define MIPS_CONF1_TLBS_SIZE    (6)
 493 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 494
 495 #define MIPS_CONF2_SA_SHF       0
 496 #define MIPS_CONF2_SA           (_ULCAST_(15) << 0)
 497 #define MIPS_CONF2_SL_SHF       4
 498 #define MIPS_CONF2_SL           (_ULCAST_(15) << 4)
 499 #define MIPS_CONF2_SS_SHF       8
 500 #define MIPS_CONF2_SS           (_ULCAST_(15) << 8)
 501 #define MIPS_CONF2_L2B          (_ULCAST_(1) << 12)
 502 #define MIPS_CONF2_SU           (_ULCAST_(15) << 12)
 503 #define MIPS_CONF2_TA           (_ULCAST_(15) << 16)
 504 #define MIPS_CONF2_TL           (_ULCAST_(15) << 20)
 505 #define MIPS_CONF2_TS           (_ULCAST_(15) << 24)
 506 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 507
 508 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 509 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 510 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 511 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 512 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 513 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 514 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 515 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 516 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 517 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 518 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 519 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 520 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 521 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 522 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 523 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 524 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 525 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 526 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 527 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 528 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 529 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 530 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 531 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 532 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 533 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 534 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 535
 536 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 537 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 538 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 539 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 540 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 541 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 542 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 543 /* bits 10:8 in FTLB-only configurations */
 544 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 545 /* bits 12:8 in VTLB-FTLB only configurations */
 546 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 547 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 548 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 549 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 550 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 551 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << 16)
 552 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 553 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 554 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 555 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 556 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 557
 558 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 559 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 560 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
 561 #define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
 562 #define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
 563 #define MIPS_CONF5_VP           (_ULCAST_(1) << 7)
 564 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 565 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
 566 #define MIPS_CONF5_L2C          (_ULCAST_(1) << 10)
 567 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 568 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 569 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 570 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 571
 572 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 573 /* proAptiv FTLB on/off bit */
 574 #define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 575 /* FTLB probability bits */
 576 #define MIPS_CONF6_FTLBP_SHIFT  (16)
 577
 578 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 579
 580 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 581
 582 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
 583 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
 584 /* FTLB probability bits for R6 */
 585 #define MIPS_CONF7_FTLBP_SHIFT  (18)
 586
 587 /* MAAR bit definitions */
 588 #define MIPS_MAAR_ADDR          ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 589 #define MIPS_MAAR_ADDR_SHIFT    12
 590 #define MIPS_MAAR_S             (_ULCAST_(1) << 1)
 591 #define MIPS_MAAR_V             (_ULCAST_(1) << 0)
 592
 593 /* CMGCRBase bit definitions */
 594 #define MIPS_CMGCRB_BASE        11
 595 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 596
 597 /*
 598  * Bits in the MIPS32 Memory Segmentation registers.
 599  */
 600 #define MIPS_SEGCFG_PA_SHIFT    9
 601 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 602 #define MIPS_SEGCFG_AM_SHIFT    4
 603 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 604 #define MIPS_SEGCFG_EU_SHIFT    3
 605 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 606 #define MIPS_SEGCFG_C_SHIFT     0
 607 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 608
 609 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
 610 #define MIPS_SEGCFG_USK         _ULCAST_(5)
 611 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
 612 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
 613 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
 614 #define MIPS_SEGCFG_MK          _ULCAST_(1)
 615 #define MIPS_SEGCFG_UK          _ULCAST_(0)
 616
 617 #define MIPS_PWFIELD_GDI_SHIFT  24
 618 #define MIPS_PWFIELD_GDI_MASK   0x3f000000
 619 #define MIPS_PWFIELD_UDI_SHIFT  18
 620 #define MIPS_PWFIELD_UDI_MASK   0x00fc0000
 621 #define MIPS_PWFIELD_MDI_SHIFT  12
 622 #define MIPS_PWFIELD_MDI_MASK   0x0003f000
 623 #define MIPS_PWFIELD_PTI_SHIFT  6
 624 #define MIPS_PWFIELD_PTI_MASK   0x00000fc0
 625 #define MIPS_PWFIELD_PTEI_SHIFT 0
 626 #define MIPS_PWFIELD_PTEI_MASK  0x0000003f
 627
 628 #define MIPS_PWSIZE_GDW_SHIFT   24
 629 #define MIPS_PWSIZE_GDW_MASK    0x3f000000
 630 #define MIPS_PWSIZE_UDW_SHIFT   18
 631 #define MIPS_PWSIZE_UDW_MASK    0x00fc0000
 632 #define MIPS_PWSIZE_MDW_SHIFT   12
 633 #define MIPS_PWSIZE_MDW_MASK    0x0003f000
 634 #define MIPS_PWSIZE_PTW_SHIFT   6
 635 #define MIPS_PWSIZE_PTW_MASK    0x00000fc0
 636 #define MIPS_PWSIZE_PTEW_SHIFT  0
 637 #define MIPS_PWSIZE_PTEW_MASK   0x0000003f
 638
 639 #define MIPS_PWCTL_PWEN_SHIFT   31
 640 #define MIPS_PWCTL_PWEN_MASK    0x80000000
 641 #define MIPS_PWCTL_DPH_SHIFT    7
 642 #define MIPS_PWCTL_DPH_MASK     0x00000080
 643 #define MIPS_PWCTL_HUGEPG_SHIFT 6
 644 #define MIPS_PWCTL_HUGEPG_MASK  0x00000060
 645 #define MIPS_PWCTL_PSN_SHIFT    0
 646 #define MIPS_PWCTL_PSN_MASK     0x0000003f
 647
 648 /* CDMMBase register bit definitions */
 649 #define MIPS_CDMMBASE_SIZE_SHIFT 0
 650 #define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
 651 #define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
 652 #define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
 653 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 654 #define MIPS_CDMMBASE_ADDR_START 15
 655
 656 /*
 657  * Bitfields in the TX39 family CP0 Configuration Register 3
 658  */
 659 #define TX39_CONF_ICS_SHIFT     19
 660 #define TX39_CONF_ICS_MASK      0x00380000
 661 #define TX39_CONF_ICS_1KB       0x00000000
 662 #define TX39_CONF_ICS_2KB       0x00080000
 663 #define TX39_CONF_ICS_4KB       0x00100000
 664 #define TX39_CONF_ICS_8KB       0x00180000
 665 #define TX39_CONF_ICS_16KB      0x00200000
 666
 667 #define TX39_CONF_DCS_SHIFT     16
 668 #define TX39_CONF_DCS_MASK      0x00070000
 669 #define TX39_CONF_DCS_1KB       0x00000000
 670 #define TX39_CONF_DCS_2KB       0x00010000
 671 #define TX39_CONF_DCS_4KB       0x00020000
 672 #define TX39_CONF_DCS_8KB       0x00030000
 673 #define TX39_CONF_DCS_16KB      0x00040000
 674
 675 #define TX39_CONF_CWFON         0x00004000
 676 #define TX39_CONF_WBON          0x00002000
 677 #define TX39_CONF_RF_SHIFT      10
 678 #define TX39_CONF_RF_MASK       0x00000c00
 679 #define TX39_CONF_DOZE          0x00000200
 680 #define TX39_CONF_HALT          0x00000100
 681 #define TX39_CONF_LOCK          0x00000080
 682 #define TX39_CONF_ICE           0x00000020
 683 #define TX39_CONF_DCE           0x00000010
 684 #define TX39_CONF_IRSIZE_SHIFT  2
 685 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 686 #define TX39_CONF_DRSIZE_SHIFT  0
 687 #define TX39_CONF_DRSIZE_MASK   0x00000003
 688
 689 /*
 690  * Interesting Bits in the R10K CP0 Branch Diagnostic Register
 691  */
 692 /* Disable Branch Target Address Cache */
 693 #define R10K_DIAG_D_BTAC        (_ULCAST_(1) << 27)
 694 /* Enable Branch Prediction Global History */
 695 #define R10K_DIAG_E_GHIST       (_ULCAST_(1) << 26)
 696 /* Disable Branch Return Cache */
 697 #define R10K_DIAG_D_BRC         (_ULCAST_(1) << 22)
 698
 699 /*
 700  * Coprocessor 1 (FPU) register names
 701  */
 702 #define CP1_REVISION    $0
 703 #define CP1_UFR         $1
 704 #define CP1_UNFR        $4
 705 #define CP1_FCCR        $25
 706 #define CP1_FEXR        $26
 707 #define CP1_FENR        $28
 708 #define CP1_STATUS      $31
 709
 710
 711 /*
 712  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 713  */
 714 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 715 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 716 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 717 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 718 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 719 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 720 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 721 #define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
 722 #define MIPS_FPIR_UFRP          (_ULCAST_(1) << 28)
 723 #define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
 724
 725 /*
 726  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
 727  */
 728 #define MIPS_FCCR_CONDX_S       0
 729 #define MIPS_FCCR_CONDX         (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
 730 #define MIPS_FCCR_COND0_S       0
 731 #define MIPS_FCCR_COND0         (_ULCAST_(1) << MIPS_FCCR_COND0_S)
 732 #define MIPS_FCCR_COND1_S       1
 733 #define MIPS_FCCR_COND1         (_ULCAST_(1) << MIPS_FCCR_COND1_S)
 734 #define MIPS_FCCR_COND2_S       2
 735 #define MIPS_FCCR_COND2         (_ULCAST_(1) << MIPS_FCCR_COND2_S)
 736 #define MIPS_FCCR_COND3_S       3
 737 #define MIPS_FCCR_COND3         (_ULCAST_(1) << MIPS_FCCR_COND3_S)
 738 #define MIPS_FCCR_COND4_S       4
 739 #define MIPS_FCCR_COND4         (_ULCAST_(1) << MIPS_FCCR_COND4_S)
 740 #define MIPS_FCCR_COND5_S       5
 741 #define MIPS_FCCR_COND5         (_ULCAST_(1) << MIPS_FCCR_COND5_S)
 742 #define MIPS_FCCR_COND6_S       6
 743 #define MIPS_FCCR_COND6         (_ULCAST_(1) << MIPS_FCCR_COND6_S)
 744 #define MIPS_FCCR_COND7_S       7
 745 #define MIPS_FCCR_COND7         (_ULCAST_(1) << MIPS_FCCR_COND7_S)
 746
 747 /*
 748  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
 749  */
 750 #define MIPS_FENR_FS_S          2
 751 #define MIPS_FENR_FS            (_ULCAST_(1) << MIPS_FENR_FS_S)
 752
 753 /*
 754  * FPU Status Register Values
 755  */
 756 #define FPU_CSR_COND_S  23                                      /* $fcc0 */
 757 #define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
 758
 759 #define FPU_CSR_FS_S    24              /* flush denormalised results to 0 */
 760 #define FPU_CSR_FS      (_ULCAST_(1) << FPU_CSR_FS_S)
 761
 762 #define FPU_CSR_CONDX_S 25                                      /* $fcc[7:1] */
 763 #define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
 764 #define FPU_CSR_COND1_S 25                                      /* $fcc1 */
 765 #define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
 766 #define FPU_CSR_COND2_S 26                                      /* $fcc2 */
 767 #define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
 768 #define FPU_CSR_COND3_S 27                                      /* $fcc3 */
 769 #define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
 770 #define FPU_CSR_COND4_S 28                                      /* $fcc4 */
 771 #define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
 772 #define FPU_CSR_COND5_S 29                                      /* $fcc5 */
 773 #define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
 774 #define FPU_CSR_COND6_S 30                                      /* $fcc6 */
 775 #define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
 776 #define FPU_CSR_COND7_S 31                                      /* $fcc7 */
 777 #define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
 778
 779 /*
 780  * Bits 22:20 of the FPU Status Register will be read as 0,
 781  * and should be written as zero.
 782  */
 783 #define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
 784
 785 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
 786 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
 787
 788 /*
 789  * X the exception cause indicator
 790  * E the exception enable
 791  * S the sticky/flag bit
 792 */
 793 #define FPU_CSR_ALL_X   0x0003f000
 794 #define FPU_CSR_UNI_X   0x00020000
 795 #define FPU_CSR_INV_X   0x00010000
 796 #define FPU_CSR_DIV_X   0x00008000
 797 #define FPU_CSR_OVF_X   0x00004000
 798 #define FPU_CSR_UDF_X   0x00002000
 799 #define FPU_CSR_INE_X   0x00001000
 800
 801 #define FPU_CSR_ALL_E   0x00000f80
 802 #define FPU_CSR_INV_E   0x00000800
 803 #define FPU_CSR_DIV_E   0x00000400
 804 #define FPU_CSR_OVF_E   0x00000200
 805 #define FPU_CSR_UDF_E   0x00000100
 806 #define FPU_CSR_INE_E   0x00000080
 807
 808 #define FPU_CSR_ALL_S   0x0000007c
 809 #define FPU_CSR_INV_S   0x00000040
 810 #define FPU_CSR_DIV_S   0x00000020
 811 #define FPU_CSR_OVF_S   0x00000010
 812 #define FPU_CSR_UDF_S   0x00000008
 813 #define FPU_CSR_INE_S   0x00000004
 814
 815 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
 816 #define FPU_CSR_RM      0x00000003
 817 #define FPU_CSR_RN      0x0     /* nearest */
 818 #define FPU_CSR_RZ      0x1     /* towards zero */
 819 #define FPU_CSR_RU      0x2     /* towards +Infinity */
 820 #define FPU_CSR_RD      0x3     /* towards -Infinity */
 821
 822
 823 #ifndef __ASSEMBLY__
 824
 825 /*
 826  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
 827  */
 828 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
 829         defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
 830 #define get_isa16_mode(x)               ((x) & 0x1)
 831 #define msk_isa16_mode(x)               ((x) & ~0x1)
 832 #define set_isa16_mode(x)               do { (x) |= 0x1; } while (0)
 833 #else
 834 #define get_isa16_mode(x)               0
 835 #define msk_isa16_mode(x)               (x)
 836 #define set_isa16_mode(x)               do { } while (0)
 837 #endif
 838
 839 /*
 840  * microMIPS instructions can be 16-bit or 32-bit in length. This
 841  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
 842  */
 843 static inline int mm_insn_16bit(u16 insn)
 844 {
 845         u16 opcode = (insn >> 10) & 0x7;
 846
 847         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
 848 }
 849
 850 /*
 851  * TLB Invalidate Flush
 852  */
 853 static inline void tlbinvf(void)
 854 {
 855         __asm__ __volatile__(
 856                 ".set push\n\t"
 857                 ".set noreorder\n\t"
 858                 ".word 0x42000004\n\t" /* tlbinvf */
 859                 ".set pop");
 860 }
 861
 862
 863 /*
 864  * Functions to access the R10000 performance counters.  These are basically
 865  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
 866  * performance counter number encoded into bits 1 ... 5 of the instruction.
 867  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
 868  * disassembler these will look like an access to sel 0 or 1.
 869  */
 870 #define read_r10k_perf_cntr(counter)                            \
 871 ({                                                              \
 872         unsigned int __res;                                     \
 873         __asm__ __volatile__(                                   \
 874         "mfpc\t%0, %1"                                          \
 875         : "=r" (__res)                                          \
 876         : "i" (counter));                                       \
 877                                                                 \
 878         __res;                                                  \
 879 })
 880
 881 #define write_r10k_perf_cntr(counter,val)                       \
 882 do {                                                            \
 883         __asm__ __volatile__(                                   \
 884         "mtpc\t%0, %1"                                          \
 885         :                                                       \
 886         : "r" (val), "i" (counter));                            \
 887 } while (0)
 888
 889 #define read_r10k_perf_event(counter)                           \
 890 ({                                                              \
 891         unsigned int __res;                                     \
 892         __asm__ __volatile__(                                   \
 893         "mfps\t%0, %1"                                          \
 894         : "=r" (__res)                                          \
 895         : "i" (counter));                                       \
 896                                                                 \
 897         __res;                                                  \
 898 })
 899
 900 #define write_r10k_perf_cntl(counter,val)                       \
 901 do {                                                            \
 902         __asm__ __volatile__(                                   \
 903         "mtps\t%0, %1"                                          \
 904         :                                                       \
 905         : "r" (val), "i" (counter));                            \
 906 } while (0)
 907
 908
 909 /*
 910  * Macros to access the system control coprocessor
 911  */
 912
 913 #define __read_32bit_c0_register(source, sel)                           \
 914 ({ unsigned int __res;                                                  \
 915         if (sel == 0)                                                   \
 916                 __asm__ __volatile__(                                   \
 917                         "mfc0\t%0, " #source "\n\t"                     \
 918                         : "=r" (__res));                                \
 919         else                                                            \
 920                 __asm__ __volatile__(                                   \
 921                         ".set\tmips32\n\t"                              \
 922                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
 923                         ".set\tmips0\n\t"                               \
 924                         : "=r" (__res));                                \
 925         __res;                                                          \
 926 })
 927
 928 #define __read_64bit_c0_register(source, sel)                           \
 929 ({ unsigned long long __res;                                            \
 930         if (sizeof(unsigned long) == 4)                                 \
 931                 __res = __read_64bit_c0_split(source, sel);             \
 932         else if (sel == 0)                                              \
 933                 __asm__ __volatile__(                                   \
 934                         ".set\tmips3\n\t"                               \
 935                         "dmfc0\t%0, " #source "\n\t"                    \
 936                         ".set\tmips0"                                   \
 937                         : "=r" (__res));                                \
 938         else                                                            \
 939                 __asm__ __volatile__(                                   \
 940                         ".set\tmips64\n\t"                              \
 941                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
 942                         ".set\tmips0"                                   \
 943                         : "=r" (__res));                                \
 944         __res;                                                          \
 945 })
 946
 947 #define __write_32bit_c0_register(register, sel, value)                 \
 948 do {                                                                    \
 949         if (sel == 0)                                                   \
 950                 __asm__ __volatile__(                                   \
 951                         "mtc0\t%z0, " #register "\n\t"                  \
 952                         : : "Jr" ((unsigned int)(value)));              \
 953         else                                                            \
 954                 __asm__ __volatile__(                                   \
 955                         ".set\tmips32\n\t"                              \
 956                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
 957                         ".set\tmips0"                                   \
 958                         : : "Jr" ((unsigned int)(value)));              \
 959 } while (0)
 960
 961 #define __write_64bit_c0_register(register, sel, value)                 \
 962 do {                                                                    \
 963         if (sizeof(unsigned long) == 4)                                 \
 964                 __write_64bit_c0_split(register, sel, value);           \
 965         else if (sel == 0)                                              \
 966                 __asm__ __volatile__(                                   \
 967                         ".set\tmips3\n\t"                               \
 968                         "dmtc0\t%z0, " #register "\n\t"                 \
 969                         ".set\tmips0"                                   \
 970                         : : "Jr" (value));                              \
 971         else                                                            \
 972                 __asm__ __volatile__(                                   \
 973                         ".set\tmips64\n\t"                              \
 974                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
 975                         ".set\tmips0"                                   \
 976                         : : "Jr" (value));                              \
 977 } while (0)
 978
 979 #define __read_ulong_c0_register(reg, sel)                              \
 980         ((sizeof(unsigned long) == 4) ?                                 \
 981         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
 982         (unsigned long) __read_64bit_c0_register(reg, sel))
 983
 984 #define __write_ulong_c0_register(reg, sel, val)                        \
 985 do {                                                                    \
 986         if (sizeof(unsigned long) == 4)                                 \
 987                 __write_32bit_c0_register(reg, sel, val);               \
 988         else                                                            \
 989                 __write_64bit_c0_register(reg, sel, val);               \
 990 } while (0)
 991
 992 /*
 993  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
 994  */
 995 #define __read_32bit_c0_ctrl_register(source)                           \
 996 ({ unsigned int __res;                                                  \
 997         __asm__ __volatile__(                                           \
 998                 "cfc0\t%0, " #source "\n\t"                             \
 999                 : "=r" (__res));                                        \
1000         __res;                                                          \
1001 })
1002
1003 #define __write_32bit_c0_ctrl_register(register, value)                 \
1004 do {                                                                    \
1005         __asm__ __volatile__(                                           \
1006                 "ctc0\t%z0, " #register "\n\t"                          \
1007                 : : "Jr" ((unsigned int)(value)));                      \
1008 } while (0)
1009
1010 /*
1011  * These versions are only needed for systems with more than 38 bits of
1012  * physical address space running the 32-bit kernel.  That's none atm :-)
1013  */
1014 #define __read_64bit_c0_split(source, sel)                              \
1015 ({                                                                      \
1016         unsigned long long __val;                                       \
1017         unsigned long __flags;                                          \
1018                                                                         \
1019         local_irq_save(__flags);                                        \
1020         if (sel == 0)                                                   \
1021                 __asm__ __volatile__(                                   \
1022                         ".set\tmips64\n\t"                              \
1023                         "dmfc0\t%M0, " #source "\n\t"                   \
1024                         "dsll\t%L0, %M0, 32\n\t"                        \
1025                         "dsra\t%M0, %M0, 32\n\t"                        \
1026                         "dsra\t%L0, %L0, 32\n\t"                        \
1027                         ".set\tmips0"                                   \
1028                         : "=r" (__val));                                \
1029         else                                                            \
1030                 __asm__ __volatile__(                                   \
1031                         ".set\tmips64\n\t"                              \
1032                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
1033                         "dsll\t%L0, %M0, 32\n\t"                        \
1034                         "dsra\t%M0, %M0, 32\n\t"                        \
1035                         "dsra\t%L0, %L0, 32\n\t"                        \
1036                         ".set\tmips0"                                   \
1037                         : "=r" (__val));                                \
1038         local_irq_restore(__flags);                                     \
1039                                                                         \
1040         __val;                                                          \
1041 })
1042
1043 #define __write_64bit_c0_split(source, sel, val)                        \
1044 do {                                                                    \
1045         unsigned long __flags;                                          \
1046                                                                         \
1047         local_irq_save(__flags);                                        \
1048         if (sel == 0)                                                   \
1049                 __asm__ __volatile__(                                   \
1050                         ".set\tmips64\n\t"                              \
1051                         "dsll\t%L0, %L0, 32\n\t"                        \
1052                         "dsrl\t%L0, %L0, 32\n\t"                        \
1053                         "dsll\t%M0, %M0, 32\n\t"                        \
1054                         "or\t%L0, %L0, %M0\n\t"                         \
1055                         "dmtc0\t%L0, " #source "\n\t"                   \
1056                         ".set\tmips0"                                   \
1057                         : : "r" (val));                                 \
1058         else                                                            \
1059                 __asm__ __volatile__(                                   \
1060                         ".set\tmips64\n\t"                              \
1061                         "dsll\t%L0, %L0, 32\n\t"                        \
1062                         "dsrl\t%L0, %L0, 32\n\t"                        \
1063                         "dsll\t%M0, %M0, 32\n\t"                        \
1064                         "or\t%L0, %L0, %M0\n\t"                         \
1065                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1066                         ".set\tmips0"                                   \
1067                         : : "r" (val));                                 \
1068         local_irq_restore(__flags);                                     \
1069 } while (0)
1070
1071 #define __readx_32bit_c0_register(source)                               \
1072 ({                                                                      \
1073         unsigned int __res;                                             \
1074                                                                         \
1075         __asm__ __volatile__(                                           \
1076         "       .set    push                                    \n"     \
1077         "       .set    noat                                    \n"     \
1078         "       .set    mips32r2                                \n"     \
1079         "       .insn                                           \n"     \
1080         "       # mfhc0 $1, %1                                  \n"     \
1081         "       .word   (0x40410000 | ((%1 & 0x1f) << 11))      \n"     \
1082         "       move    %0, $1                                  \n"     \
1083         "       .set    pop                                     \n"     \
1084         : "=r" (__res)                                                  \
1085         : "i" (source));                                                \
1086         __res;                                                          \
1087 })
1088
1089 #define __writex_32bit_c0_register(register, value)                     \
1090 ({                                                                      \
1091         __asm__ __volatile__(                                           \
1092         "       .set    push                                    \n"     \
1093         "       .set    noat                                    \n"     \
1094         "       .set    mips32r2                                \n"     \
1095         "       move    $1, %0                                  \n"     \
1096         "       # mthc0 $1, %1                                  \n"     \
1097         "       .insn                                           \n"     \
1098         "       .word   (0x40c10000 | ((%1 & 0x1f) << 11))      \n"     \
1099         "       .set    pop                                     \n"     \
1100         :                                                               \
1101         : "r" (value), "i" (register));                                 \
1102 })
1103
1104 #define read_c0_index()         __read_32bit_c0_register($0, 0)
1105 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
1106
1107 #define read_c0_random()        __read_32bit_c0_register($1, 0)
1108 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
1109
1110 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
1111 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
1112
1113 #define readx_c0_entrylo0()     __readx_32bit_c0_register(2)
1114 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1115
1116 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
1117 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
1118
1119 #define readx_c0_entrylo1()     __readx_32bit_c0_register(3)
1120 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1121
1122 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
1123 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
1124
1125 #define read_c0_context()       __read_ulong_c0_register($4, 0)
1126 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
1127
1128 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
1129 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1130
1131 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
1132 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
1133
1134 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
1135 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1136
1137 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
1138 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
1139
1140 #define read_c0_info()          __read_32bit_c0_register($7, 0)
1141
1142 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
1143 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
1144
1145 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
1146 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
1147
1148 #define read_c0_count()         __read_32bit_c0_register($9, 0)
1149 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
1150
1151 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
1152 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
1153
1154 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
1155 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
1156
1157 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
1158 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
1159
1160 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
1161 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
1162
1163 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
1164 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
1165
1166 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
1167 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
1168
1169 #define read_c0_status()        __read_32bit_c0_register($12, 0)
1170
1171 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1172
1173 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1174 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1175
1176 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1177 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1178
1179 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
1180
1181 #define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
1182
1183 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1184 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1185 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1186 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1187 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1188 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1189 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1190 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1191 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1192 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1193 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1194 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1195 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1196 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1197 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1198 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1199
1200 #define read_c0_lladdr()        __read_ulong_c0_register($17, 0)
1201 #define write_c0_lladdr(val)    __write_ulong_c0_register($17, 0, val)
1202 #define read_c0_maar()          __read_ulong_c0_register($17, 1)
1203 #define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
1204 #define read_c0_maari()         __read_32bit_c0_register($17, 2)
1205 #define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
1206
1207 /*
1208  * The WatchLo register.  There may be up to 8 of them.
1209  */
1210 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1211 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1212 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1213 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1214 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1215 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1216 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1217 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1218 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1219 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1220 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1221 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1222 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1223 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1224 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1225 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1226
1227 /*
1228  * The WatchHi register.  There may be up to 8 of them.
1229  */
1230 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1231 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1232 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1233 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1234 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1235 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1236 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1237 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1238
1239 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1240 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1241 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1242 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1243 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1244 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1245 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1246 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1247
1248 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1249 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1250
1251 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1252 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1253
1254 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1255 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1256
1257 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1258 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1259
1260 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1261 #define read_c0_r10k_diag()     __read_64bit_c0_register($22, 0)
1262 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1263
1264 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1265 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1266
1267 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1268 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1269
1270 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1271 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1272
1273 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1274 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1275
1276 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1277 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1278
1279 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1280 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1281
1282 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1283 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1284
1285 /*
1286  * MIPS32 / MIPS64 performance counters
1287  */
1288 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1289 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1290 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1291 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1292 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1293 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1294 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1295 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1296 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1297 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1298 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1299 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1300 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1301 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1302 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1303 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1304 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1305 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1306 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1307 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1308 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1309 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1310 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1311 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1312
1313 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1314 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1315
1316 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1317 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1318
1319 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1320
1321 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1322 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1323
1324 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1325 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1326
1327 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1328 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1329
1330 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1331 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1332
1333 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1334 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1335
1336 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1337 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1338
1339 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1340 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1341
1342 /* MIPSR2 */
1343 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1344 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1345
1346 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1347 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1348
1349 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1350 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1351
1352 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1353 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1354
1355 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1356 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1357
1358 #define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
1359 #define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
1360
1361 /* MIPSR3 */
1362 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1363 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1364
1365 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1366 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1367
1368 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1369 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1370
1371 /* Hardware Page Table Walker */
1372 #define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
1373 #define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
1374
1375 #define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
1376 #define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
1377
1378 #define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
1379 #define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
1380
1381 #define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
1382 #define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
1383
1384 /* Cavium OCTEON (cnMIPS) */
1385 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1386 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1387
1388 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1389 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1390
1391 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1392 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1393 /*
1394  * The cacheerr registers are not standardized.  On OCTEON, they are
1395  * 64 bits wide.
1396  */
1397 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1398 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1399
1400 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1401 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1402
1403 /* BMIPS3300 */
1404 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1405 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1406
1407 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1408 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1409
1410 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1411 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1412
1413 /* BMIPS43xx */
1414 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1415 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1416
1417 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1418 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1419
1420 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1421 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1422
1423 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1424 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1425
1426 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1427 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1428
1429 /* BMIPS5000 */
1430 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1431 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1432
1433 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1434 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1435
1436 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1437 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1438
1439 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1440 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1441
1442 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1443 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1444
1445 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1446 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1447
1448 /*
1449  * Macros to access the floating point coprocessor control registers
1450  */
1451 #define _read_32bit_cp1_register(source, gas_hardfloat)                 \
1452 ({                                                                      \
1453         unsigned int __res;                                             \
1454                                                                         \
1455         __asm__ __volatile__(                                           \
1456         "       .set    push                                    \n"     \
1457         "       .set    reorder                                 \n"     \
1458         "       # gas fails to assemble cfc1 for some archs,    \n"     \
1459         "       # like Octeon.                                  \n"     \
1460         "       .set    mips1                                   \n"     \
1461         "       "STR(gas_hardfloat)"                            \n"     \
1462         "       cfc1    %0,"STR(source)"                        \n"     \
1463         "       .set    pop                                     \n"     \
1464         : "=r" (__res));                                                \
1465         __res;                                                          \
1466 })
1467
1468 #define _write_32bit_cp1_register(dest, val, gas_hardfloat)             \
1469 ({                                                                      \
1470         __asm__ __volatile__(                                           \
1471         "       .set    push                                    \n"     \
1472         "       .set    reorder                                 \n"     \
1473         "       "STR(gas_hardfloat)"                            \n"     \
1474         "       ctc1    %0,"STR(dest)"                          \n"     \
1475         "       .set    pop                                     \n"     \
1476         : : "r" (val));                                                 \
1477 })
1478
1479 #ifdef GAS_HAS_SET_HARDFLOAT
1480 #define read_32bit_cp1_register(source)                                 \
1481         _read_32bit_cp1_register(source, .set hardfloat)
1482 #define write_32bit_cp1_register(dest, val)                             \
1483         _write_32bit_cp1_register(dest, val, .set hardfloat)
1484 #else
1485 #define read_32bit_cp1_register(source)                                 \
1486         _read_32bit_cp1_register(source, )
1487 #define write_32bit_cp1_register(dest, val)                             \
1488         _write_32bit_cp1_register(dest, val, )
1489 #endif
1490
1491 #ifdef HAVE_AS_DSP
1492 #define rddsp(mask)                                                     \
1493 ({                                                                      \
1494         unsigned int __dspctl;                                          \
1495                                                                         \
1496         __asm__ __volatile__(                                           \
1497         "       .set push                                       \n"     \
1498         "       .set dsp                                        \n"     \
1499         "       rddsp   %0, %x1                                 \n"     \
1500         "       .set pop                                        \n"     \
1501         : "=r" (__dspctl)                                               \
1502         : "i" (mask));                                                  \
1503         __dspctl;                                                       \
1504 })
1505
1506 #define wrdsp(val, mask)                                                \
1507 ({                                                                      \
1508         __asm__ __volatile__(                                           \
1509         "       .set push                                       \n"     \
1510         "       .set dsp                                        \n"     \
1511         "       wrdsp   %0, %x1                                 \n"     \
1512         "       .set pop                                        \n"     \
1513         :                                                               \
1514         : "r" (val), "i" (mask));                                       \
1515 })
1516
1517 #define mflo0()                                                         \
1518 ({                                                                      \
1519         long mflo0;                                                     \
1520         __asm__(                                                        \
1521         "       .set push                                       \n"     \
1522         "       .set dsp                                        \n"     \
1523         "       mflo %0, $ac0                                   \n"     \
1524         "       .set pop                                        \n"     \
1525         : "=r" (mflo0));                                                \
1526         mflo0;                                                          \
1527 })
1528
1529 #define mflo1()                                                         \
1530 ({                                                                      \
1531         long mflo1;                                                     \
1532         __asm__(                                                        \
1533         "       .set push                                       \n"     \
1534         "       .set dsp                                        \n"     \
1535         "       mflo %0, $ac1                                   \n"     \
1536         "       .set pop                                        \n"     \
1537         : "=r" (mflo1));                                                \
1538         mflo1;                                                          \
1539 })
1540
1541 #define mflo2()                                                         \
1542 ({                                                                      \
1543         long mflo2;                                                     \
1544         __asm__(                                                        \
1545         "       .set push                                       \n"     \
1546         "       .set dsp                                        \n"     \
1547         "       mflo %0, $ac2                                   \n"     \
1548         "       .set pop                                        \n"     \
1549         : "=r" (mflo2));                                                \
1550         mflo2;                                                          \
1551 })
1552
1553 #define mflo3()                                                         \
1554 ({                                                                      \
1555         long mflo3;                                                     \
1556         __asm__(                                                        \
1557         "       .set push                                       \n"     \
1558         "       .set dsp                                        \n"     \
1559         "       mflo %0, $ac3                                   \n"     \
1560         "       .set pop                                        \n"     \
1561         : "=r" (mflo3));                                                \
1562         mflo3;                                                          \
1563 })
1564
1565 #define mfhi0()                                                         \
1566 ({                                                                      \
1567         long mfhi0;                                                     \
1568         __asm__(                                                        \
1569         "       .set push                                       \n"     \
1570         "       .set dsp                                        \n"     \
1571         "       mfhi %0, $ac0                                   \n"     \
1572         "       .set pop                                        \n"     \
1573         : "=r" (mfhi0));                                                \
1574         mfhi0;                                                          \
1575 })
1576
1577 #define mfhi1()                                                         \
1578 ({                                                                      \
1579         long mfhi1;                                                     \
1580         __asm__(                                                        \
1581         "       .set push                                       \n"     \
1582         "       .set dsp                                        \n"     \
1583         "       mfhi %0, $ac1                                   \n"     \
1584         "       .set pop                                        \n"     \
1585         : "=r" (mfhi1));                                                \
1586         mfhi1;                                                          \
1587 })
1588
1589 #define mfhi2()                                                         \
1590 ({                                                                      \
1591         long mfhi2;                                                     \
1592         __asm__(                                                        \
1593         "       .set push                                       \n"     \
1594         "       .set dsp                                        \n"     \
1595         "       mfhi %0, $ac2                                   \n"     \
1596         "       .set pop                                        \n"     \
1597         : "=r" (mfhi2));                                                \
1598         mfhi2;                                                          \
1599 })
1600
1601 #define mfhi3()                                                         \
1602 ({                                                                      \
1603         long mfhi3;                                                     \
1604         __asm__(                                                        \
1605         "       .set push                                       \n"     \
1606         "       .set dsp                                        \n"     \
1607         "       mfhi %0, $ac3                                   \n"     \
1608         "       .set pop                                        \n"     \
1609         : "=r" (mfhi3));                                                \
1610         mfhi3;                                                          \
1611 })
1612
1613
1614 #define mtlo0(x)                                                        \
1615 ({                                                                      \
1616         __asm__(                                                        \
1617         "       .set push                                       \n"     \
1618         "       .set dsp                                        \n"     \
1619         "       mtlo %0, $ac0                                   \n"     \
1620         "       .set pop                                        \n"     \
1621         :                                                               \
1622         : "r" (x));                                                     \
1623 })
1624
1625 #define mtlo1(x)                                                        \
1626 ({                                                                      \
1627         __asm__(                                                        \
1628         "       .set push                                       \n"     \
1629         "       .set dsp                                        \n"     \
1630         "       mtlo %0, $ac1                                   \n"     \
1631         "       .set pop                                        \n"     \
1632         :                                                               \
1633         : "r" (x));                                                     \
1634 })
1635
1636 #define mtlo2(x)                                                        \
1637 ({                                                                      \
1638         __asm__(                                                        \
1639         "       .set push                                       \n"     \
1640         "       .set dsp                                        \n"     \
1641         "       mtlo %0, $ac2                                   \n"     \
1642         "       .set pop                                        \n"     \
1643         :                                                               \
1644         : "r" (x));                                                     \
1645 })
1646
1647 #define mtlo3(x)                                                        \
1648 ({                                                                      \
1649         __asm__(                                                        \
1650         "       .set push                                       \n"     \
1651         "       .set dsp                                        \n"     \
1652         "       mtlo %0, $ac3                                   \n"     \
1653         "       .set pop                                        \n"     \
1654         :                                                               \
1655         : "r" (x));                                                     \
1656 })
1657
1658 #define mthi0(x)                                                        \
1659 ({                                                                      \
1660         __asm__(                                                        \
1661         "       .set push                                       \n"     \
1662         "       .set dsp                                        \n"     \
1663         "       mthi %0, $ac0                                   \n"     \
1664         "       .set pop                                        \n"     \
1665         :                                                               \
1666         : "r" (x));                                                     \
1667 })
1668
1669 #define mthi1(x)                                                        \
1670 ({                                                                      \
1671         __asm__(                                                        \
1672         "       .set push                                       \n"     \
1673         "       .set dsp                                        \n"     \
1674         "       mthi %0, $ac1                                   \n"     \
1675         "       .set pop                                        \n"     \
1676         :                                                               \
1677         : "r" (x));                                                     \
1678 })
1679
1680 #define mthi2(x)                                                        \
1681 ({                                                                      \
1682         __asm__(                                                        \
1683         "       .set push                                       \n"     \
1684         "       .set dsp                                        \n"     \
1685         "       mthi %0, $ac2                                   \n"     \
1686         "       .set pop                                        \n"     \
1687         :                                                               \
1688         : "r" (x));                                                     \
1689 })
1690
1691 #define mthi3(x)                                                        \
1692 ({                                                                      \
1693         __asm__(                                                        \
1694         "       .set push                                       \n"     \
1695         "       .set dsp                                        \n"     \
1696         "       mthi %0, $ac3                                   \n"     \
1697         "       .set pop                                        \n"     \
1698         :                                                               \
1699         : "r" (x));                                                     \
1700 })
1701
1702 #else
1703
1704 #ifdef CONFIG_CPU_MICROMIPS
1705 #define rddsp(mask)                                                     \
1706 ({                                                                      \
1707         unsigned int __res;                                             \
1708                                                                         \
1709         __asm__ __volatile__(                                           \
1710         "       .set    push                                    \n"     \
1711         "       .set    noat                                    \n"     \
1712         "       # rddsp $1, %x1                                 \n"     \
1713         "       .hword  ((0x0020067c | (%x1 << 14)) >> 16)      \n"     \
1714         "       .hword  ((0x0020067c | (%x1 << 14)) & 0xffff)   \n"     \
1715         "       move    %0, $1                                  \n"     \
1716         "       .set    pop                                     \n"     \
1717         : "=r" (__res)                                                  \
1718         : "i" (mask));                                                  \
1719         __res;                                                          \
1720 })
1721
1722 #define wrdsp(val, mask)                                                \
1723 ({                                                                      \
1724         __asm__ __volatile__(                                           \
1725         "       .set    push                                    \n"     \
1726         "       .set    noat                                    \n"     \
1727         "       move    $1, %0                                  \n"     \
1728         "       # wrdsp $1, %x1                                 \n"     \
1729         "       .hword  ((0x0020167c | (%x1 << 14)) >> 16)      \n"     \
1730         "       .hword  ((0x0020167c | (%x1 << 14)) & 0xffff)   \n"     \
1731         "       .set    pop                                     \n"     \
1732         :                                                               \
1733         : "r" (val), "i" (mask));                                       \
1734 })
1735
1736 #define _umips_dsp_mfxxx(ins)                                           \
1737 ({                                                                      \
1738         unsigned long __treg;                                           \
1739                                                                         \
1740         __asm__ __volatile__(                                           \
1741         "       .set    push                                    \n"     \
1742         "       .set    noat                                    \n"     \
1743         "       .hword  0x0001                                  \n"     \
1744         "       .hword  %x1                                     \n"     \
1745         "       move    %0, $1                                  \n"     \
1746         "       .set    pop                                     \n"     \
1747         : "=r" (__treg)                                                 \
1748         : "i" (ins));                                                   \
1749         __treg;                                                         \
1750 })
1751
1752 #define _umips_dsp_mtxxx(val, ins)                                      \
1753 ({                                                                      \
1754         __asm__ __volatile__(                                           \
1755         "       .set    push                                    \n"     \
1756         "       .set    noat                                    \n"     \
1757         "       move    $1, %0                                  \n"     \
1758         "       .hword  0x0001                                  \n"     \
1759         "       .hword  %x1                                     \n"     \
1760         "       .set    pop                                     \n"     \
1761         :                                                               \
1762         : "r" (val), "i" (ins));                                        \
1763 })
1764
1765 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1766 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1767
1768 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1769 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1770
1771 #define mflo0() _umips_dsp_mflo(0)
1772 #define mflo1() _umips_dsp_mflo(1)
1773 #define mflo2() _umips_dsp_mflo(2)
1774 #define mflo3() _umips_dsp_mflo(3)
1775
1776 #define mfhi0() _umips_dsp_mfhi(0)
1777 #define mfhi1() _umips_dsp_mfhi(1)
1778 #define mfhi2() _umips_dsp_mfhi(2)
1779 #define mfhi3() _umips_dsp_mfhi(3)
1780
1781 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1782 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1783 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1784 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1785
1786 #define mthi0(x) _umips_dsp_mthi(x, 0)
1787 #define mthi1(x) _umips_dsp_mthi(x, 1)
1788 #define mthi2(x) _umips_dsp_mthi(x, 2)
1789 #define mthi3(x) _umips_dsp_mthi(x, 3)
1790
1791 #else  /* !CONFIG_CPU_MICROMIPS */
1792 #define rddsp(mask)                                                     \
1793 ({                                                                      \
1794         unsigned int __res;                                             \
1795                                                                         \
1796         __asm__ __volatile__(                                           \
1797         "       .set    push                            \n"             \
1798         "       .set    noat                            \n"             \
1799         "       # rddsp $1, %x1                         \n"             \
1800         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
1801         "       move    %0, $1                          \n"             \
1802         "       .set    pop                             \n"             \
1803         : "=r" (__res)                                                  \
1804         : "i" (mask));                                                  \
1805         __res;                                                          \
1806 })
1807
1808 #define wrdsp(val, mask)                                                \
1809 ({                                                                      \
1810         __asm__ __volatile__(                                           \
1811         "       .set    push                                    \n"     \
1812         "       .set    noat                                    \n"     \
1813         "       move    $1, %0                                  \n"     \
1814         "       # wrdsp $1, %x1                                 \n"     \
1815         "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
1816         "       .set    pop                                     \n"     \
1817         :                                                               \
1818         : "r" (val), "i" (mask));                                       \
1819 })
1820
1821 #define _dsp_mfxxx(ins)                                                 \
1822 ({                                                                      \
1823         unsigned long __treg;                                           \
1824                                                                         \
1825         __asm__ __volatile__(                                           \
1826         "       .set    push                                    \n"     \
1827         "       .set    noat                                    \n"     \
1828         "       .word   (0x00000810 | %1)                       \n"     \
1829         "       move    %0, $1                                  \n"     \
1830         "       .set    pop                                     \n"     \
1831         : "=r" (__treg)                                                 \
1832         : "i" (ins));                                                   \
1833         __treg;                                                         \
1834 })
1835
1836 #define _dsp_mtxxx(val, ins)                                            \
1837 ({                                                                      \
1838         __asm__ __volatile__(                                           \
1839         "       .set    push                                    \n"     \
1840         "       .set    noat                                    \n"     \
1841         "       move    $1, %0                                  \n"     \
1842         "       .word   (0x00200011 | %1)                       \n"     \
1843         "       .set    pop                                     \n"     \
1844         :                                                               \
1845         : "r" (val), "i" (ins));                                        \
1846 })
1847
1848 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1849 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1850
1851 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1852 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1853
1854 #define mflo0() _dsp_mflo(0)
1855 #define mflo1() _dsp_mflo(1)
1856 #define mflo2() _dsp_mflo(2)
1857 #define mflo3() _dsp_mflo(3)
1858
1859 #define mfhi0() _dsp_mfhi(0)
1860 #define mfhi1() _dsp_mfhi(1)
1861 #define mfhi2() _dsp_mfhi(2)
1862 #define mfhi3() _dsp_mfhi(3)
1863
1864 #define mtlo0(x) _dsp_mtlo(x, 0)
1865 #define mtlo1(x) _dsp_mtlo(x, 1)
1866 #define mtlo2(x) _dsp_mtlo(x, 2)
1867 #define mtlo3(x) _dsp_mtlo(x, 3)
1868
1869 #define mthi0(x) _dsp_mthi(x, 0)
1870 #define mthi1(x) _dsp_mthi(x, 1)
1871 #define mthi2(x) _dsp_mthi(x, 2)
1872 #define mthi3(x) _dsp_mthi(x, 3)
1873
1874 #endif /* CONFIG_CPU_MICROMIPS */
1875 #endif
1876
1877 /*
1878  * TLB operations.
1879  *
1880  * It is responsibility of the caller to take care of any TLB hazards.
1881  */
1882 static inline void tlb_probe(void)
1883 {
1884         __asm__ __volatile__(
1885                 ".set noreorder\n\t"
1886                 "tlbp\n\t"
1887                 ".set reorder");
1888 }
1889
1890 static inline void tlb_read(void)
1891 {
1892 #if MIPS34K_MISSED_ITLB_WAR
1893         int res = 0;
1894
1895         __asm__ __volatile__(
1896         "       .set    push                                    \n"
1897         "       .set    noreorder                               \n"
1898         "       .set    noat                                    \n"
1899         "       .set    mips32r2                                \n"
1900         "       .word   0x41610001              # dvpe $1       \n"
1901         "       move    %0, $1                                  \n"
1902         "       ehb                                             \n"
1903         "       .set    pop                                     \n"
1904         : "=r" (res));
1905
1906         instruction_hazard();
1907 #endif
1908
1909         __asm__ __volatile__(
1910                 ".set noreorder\n\t"
1911                 "tlbr\n\t"
1912                 ".set reorder");
1913
1914 #if MIPS34K_MISSED_ITLB_WAR
1915         if ((res & _ULCAST_(1)))
1916                 __asm__ __volatile__(
1917                 "       .set    push                            \n"
1918                 "       .set    noreorder                       \n"
1919                 "       .set    noat                            \n"
1920                 "       .set    mips32r2                        \n"
1921                 "       .word   0x41600021      # evpe          \n"
1922                 "       ehb                                     \n"
1923                 "       .set    pop                             \n");
1924 #endif
1925 }
1926
1927 static inline void tlb_write_indexed(void)
1928 {
1929         __asm__ __volatile__(
1930                 ".set noreorder\n\t"
1931                 "tlbwi\n\t"
1932                 ".set reorder");
1933 }
1934
1935 static inline void tlb_write_random(void)
1936 {
1937         __asm__ __volatile__(
1938                 ".set noreorder\n\t"
1939                 "tlbwr\n\t"
1940                 ".set reorder");
1941 }
1942
1943 /*
1944  * Manipulate bits in a c0 register.
1945  */
1946 #define __BUILD_SET_C0(name)                                    \
1947 static inline unsigned int                                      \
1948 set_c0_##name(unsigned int set)                                 \
1949 {                                                               \
1950         unsigned int res, new;                                  \
1951                                                                 \
1952         res = read_c0_##name();                                 \
1953         new = res | set;                                        \
1954         write_c0_##name(new);                                   \
1955                                                                 \
1956         return res;                                             \
1957 }                                                               \
1958                                                                 \
1959 static inline unsigned int                                      \
1960 clear_c0_##name(unsigned int clear)                             \
1961 {                                                               \
1962         unsigned int res, new;                                  \
1963                                                                 \
1964         res = read_c0_##name();                                 \
1965         new = res & ~clear;                                     \
1966         write_c0_##name(new);                                   \
1967                                                                 \
1968         return res;                                             \
1969 }                                                               \
1970                                                                 \
1971 static inline unsigned int                                      \
1972 change_c0_##name(unsigned int change, unsigned int val)         \
1973 {                                                               \
1974         unsigned int res, new;                                  \
1975                                                                 \
1976         res = read_c0_##name();                                 \
1977         new = res & ~change;                                    \
1978         new |= (val & change);                                  \
1979         write_c0_##name(new);                                   \
1980                                                                 \
1981         return res;                                             \
1982 }
1983
1984 __BUILD_SET_C0(status)
1985 __BUILD_SET_C0(cause)
1986 __BUILD_SET_C0(config)
1987 __BUILD_SET_C0(config5)
1988 __BUILD_SET_C0(intcontrol)
1989 __BUILD_SET_C0(intctl)
1990 __BUILD_SET_C0(srsmap)
1991 __BUILD_SET_C0(pagegrain)
1992 __BUILD_SET_C0(brcm_config_0)
1993 __BUILD_SET_C0(brcm_bus_pll)
1994 __BUILD_SET_C0(brcm_reset)
1995 __BUILD_SET_C0(brcm_cmt_intr)
1996 __BUILD_SET_C0(brcm_cmt_ctrl)
1997 __BUILD_SET_C0(brcm_config)
1998 __BUILD_SET_C0(brcm_mode)
1999
2000 /*
2001  * Return low 10 bits of ebase.
2002  * Note that under KVM (MIPSVZ) this returns vcpu id.
2003  */
2004 static inline unsigned int get_ebase_cpunum(void)
2005 {
2006         return read_c0_ebase() & 0x3ff;
2007 }
2008
2009 #endif /* !__ASSEMBLY__ */
2010
2011 #endif /* _ASM_MIPSREGS_H */