2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
7 * Copyright (C) 1999 by Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc.
9 * Copyright (C) 2002 Maciej W. Rozycki
11 * Some useful macros for MIPS assembler code
13 * Some of the routines below contain useless nops that will be optimized
14 * away by gas in -O mode. These nops are however required to fill delay
15 * slots in noreorder mode.
20 #include <asm/sgidefs.h>
24 #define __CAT(str1, str2) str1##str2
26 #define __CAT(str1, str2) str1/**/str2
28 #define CAT(str1, str2) __CAT(str1, str2)
32 * PIC specific declarations
33 * Not used for the kernel but here seems to be the right place.
36 #define CPRESTORE(register) \
38 #define CPADD(register) \
40 #define CPLOAD(register) \
43 #define CPRESTORE(register)
44 #define CPADD(register)
45 #define CPLOAD(register)
48 #define ENTRY(symbol) \
50 .type symbol, @function; \
55 * LEAF - declare leaf routine
57 #define LEAF(symbol) \
60 .type symbol, @function; \
62 .section .text.symbol, "x"; \
63 symbol: .frame sp, 0, ra
66 * NESTED - declare nested routine entry point
68 #define NESTED(symbol, framesize, rpc) \
71 .type symbol, @function; \
73 .section .text.symbol, "x"; \
74 symbol: .frame sp, framesize, rpc
77 * END - mark end of function
79 #define END(function) \
81 .size function, .-function
84 * EXPORT - export definition of symbol
86 #define EXPORT(symbol) \
91 * FEXPORT - export definition of a function symbol
93 #define FEXPORT(symbol) \
95 .type symbol, @function; \
99 * ABS - export absolute symbol
101 #define ABS(symbol,value) \
115 * Print formatted string
118 #define PRINT(string) \
126 #define PRINT(string)
130 .pushsection .data; \
137 #define TTABLE(string) \
138 .pushsection .text; \
141 .pushsection .data; \
146 * MIPS IV pref instruction.
147 * Use with .set noreorder only!
149 * MIPS IV implementations are free to treat this as a nop. The R5000
150 * is one of them. So we should have an option not to use this instruction.
152 #ifdef CONFIG_CPU_HAS_PREFETCH
154 #define PREF(hint,addr) \
160 #define PREFX(hint,addr) \
166 #else /* !CONFIG_CPU_HAS_PREFETCH */
168 #define PREF(hint, addr)
169 #define PREFX(hint, addr)
171 #endif /* !CONFIG_CPU_HAS_PREFETCH */
174 * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
176 #if (_MIPS_ISA == _MIPS_ISA_MIPS1)
177 #define MOVN(rd, rs, rt) \
184 #define MOVZ(rd, rs, rt) \
191 #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
192 #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
193 #define MOVN(rd, rs, rt) \
200 #define MOVZ(rd, rs, rt) \
207 #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
208 #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
209 (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
210 #define MOVN(rd, rs, rt) \
212 #define MOVZ(rd, rs, rt) \
214 #endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
219 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
223 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
229 * Macros to handle different pointer/register sizes for 32/64-bit code
242 * Use the following macros in assemblercode to load/store registers,
245 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
248 #define REG_SUBU subu
249 #define REG_ADDU addu
251 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
254 #define REG_SUBU dsubu
255 #define REG_ADDU daddu
259 * How to add/sub/load/store/shift C int variables.
261 #if (_MIPS_SZINT == 32)
263 #define INT_ADDU addu
264 #define INT_ADDI addi
265 #define INT_ADDIU addiu
267 #define INT_SUBU subu
271 #define INT_SLLV sllv
273 #define INT_SRLV srlv
275 #define INT_SRAV srav
278 #if (_MIPS_SZINT == 64)
280 #define INT_ADDU daddu
281 #define INT_ADDI daddi
282 #define INT_ADDIU daddiu
284 #define INT_SUBU dsubu
288 #define INT_SLLV dsllv
290 #define INT_SRLV dsrlv
292 #define INT_SRAV dsrav
296 * How to add/sub/load/store/shift C long variables.
298 #if (_MIPS_SZLONG == 32)
300 #define LONG_ADDU addu
301 #define LONG_ADDI addi
302 #define LONG_ADDIU addiu
304 #define LONG_SUBU subu
308 #define LONG_SLLV sllv
310 #define LONG_SRLV srlv
312 #define LONG_SRAV srav
320 #if (_MIPS_SZLONG == 64)
321 #define LONG_ADD dadd
322 #define LONG_ADDU daddu
323 #define LONG_ADDI daddi
324 #define LONG_ADDIU daddiu
325 #define LONG_SUB dsub
326 #define LONG_SUBU dsubu
329 #define LONG_SLL dsll
330 #define LONG_SLLV dsllv
331 #define LONG_SRL dsrl
332 #define LONG_SRLV dsrlv
333 #define LONG_SRA dsra
334 #define LONG_SRAV dsrav
343 * How to add/sub/load/store/shift pointers.
345 #if (_MIPS_SZPTR == 32)
347 #define PTR_ADDU addu
348 #define PTR_ADDI addi
349 #define PTR_ADDIU addiu
351 #define PTR_SUBU subu
357 #define PTR_SLLV sllv
359 #define PTR_SRLV srlv
361 #define PTR_SRAV srav
363 #define PTR_SCALESHIFT 2
370 #if (_MIPS_SZPTR == 64)
372 #define PTR_ADDU daddu
373 #define PTR_ADDI daddi
374 #define PTR_ADDIU daddiu
376 #define PTR_SUBU dsubu
382 #define PTR_SLLV dsllv
384 #define PTR_SRLV dsrlv
386 #define PTR_SRAV dsrav
388 #define PTR_SCALESHIFT 3
396 * Some cp0 registers were extended to 64bit for MIPS III.
398 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
402 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
407 #define SSNOP sll zero, zero, 1
409 #ifdef CONFIG_SGI_IP28
410 /* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
411 #include <asm/cacheops.h>
412 #define R10KCBARRIER(addr) cache CACHE_BARRIER, addr;
414 #define R10KCBARRIER(addr)
417 #endif /* __ASM_ASM_H */