1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
4 * Copyright (C) 1999 by Silicon Graphics, Inc.
5 * Copyright (C) 2001 MIPS Technologies, Inc.
6 * Copyright (C) 2002 Maciej W. Rozycki
8 * Some useful macros for MIPS assembler code
10 * Some of the routines below contain useless nops that will be optimized
11 * away by gas in -O mode. These nops are however required to fill delay
12 * slots in noreorder mode.
17 #include <asm/sgidefs.h>
21 #define __CAT(str1, str2) str1##str2
23 #define __CAT(str1, str2) str1/**/str2
25 #define CAT(str1, str2) __CAT(str1, str2)
29 * PIC specific declarations
30 * Not used for the kernel but here seems to be the right place.
33 #define CPRESTORE(register) \
35 #define CPADD(register) \
37 #define CPLOAD(register) \
40 #define CPRESTORE(register)
41 #define CPADD(register)
42 #define CPLOAD(register)
45 #define ENTRY(symbol) \
47 .type symbol, @function; \
52 * LEAF - declare leaf routine
54 #define LEAF(symbol) \
57 .type symbol, @function; \
59 .section .text.symbol, "x"; \
60 symbol: .frame sp, 0, ra
63 * NESTED - declare nested routine entry point
65 #define NESTED(symbol, framesize, rpc) \
68 .type symbol, @function; \
70 .section .text.symbol, "x"; \
71 symbol: .frame sp, framesize, rpc
74 * END - mark end of function
76 #define END(function) \
78 .size function, .-function
81 * EXPORT - export definition of symbol
83 #define EXPORT(symbol) \
88 * FEXPORT - export definition of a function symbol
90 #define FEXPORT(symbol) \
92 .type symbol, @function; \
96 * ABS - export absolute symbol
98 #define ABS(symbol,value) \
112 * Print formatted string
115 #define PRINT(string) \
123 #define PRINT(string)
127 .pushsection .data; \
134 #define TTABLE(string) \
135 .pushsection .text; \
138 .pushsection .data; \
143 * MIPS IV pref instruction.
144 * Use with .set noreorder only!
146 * MIPS IV implementations are free to treat this as a nop. The R5000
147 * is one of them. So we should have an option not to use this instruction.
149 #ifdef CONFIG_CPU_HAS_PREFETCH
151 #define PREF(hint, addr) \
157 #define PREFE(hint, addr) \
164 #define PREFX(hint, addr) \
170 #else /* !CONFIG_CPU_HAS_PREFETCH */
172 #define PREF(hint, addr)
173 #define PREFE(hint, addr)
174 #define PREFX(hint, addr)
176 #endif /* !CONFIG_CPU_HAS_PREFETCH */
179 * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
181 #if (_MIPS_ISA == _MIPS_ISA_MIPS1)
182 #define MOVN(rd, rs, rt) \
189 #define MOVZ(rd, rs, rt) \
196 #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
197 #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
198 #define MOVN(rd, rs, rt) \
205 #define MOVZ(rd, rs, rt) \
212 #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
213 #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
214 (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
215 #define MOVN(rd, rs, rt) \
217 #define MOVZ(rd, rs, rt) \
219 #endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
224 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
228 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
234 * Macros to handle different pointer/register sizes for 32/64-bit code
247 * Use the following macros in assemblercode to load/store registers,
250 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
253 #define REG_SUBU subu
254 #define REG_ADDU addu
256 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
259 #define REG_SUBU dsubu
260 #define REG_ADDU daddu
264 * How to add/sub/load/store/shift C int variables.
266 #if (_MIPS_SZINT == 32)
268 #define INT_ADDU addu
269 #define INT_ADDI addi
270 #define INT_ADDIU addiu
272 #define INT_SUBU subu
276 #define INT_SLLV sllv
278 #define INT_SRLV srlv
280 #define INT_SRAV srav
283 #if (_MIPS_SZINT == 64)
285 #define INT_ADDU daddu
286 #define INT_ADDI daddi
287 #define INT_ADDIU daddiu
289 #define INT_SUBU dsubu
293 #define INT_SLLV dsllv
295 #define INT_SRLV dsrlv
297 #define INT_SRAV dsrav
301 * How to add/sub/load/store/shift C long variables.
303 #if (_MIPS_SZLONG == 32)
305 #define LONG_ADDU addu
306 #define LONG_ADDI addi
307 #define LONG_ADDIU addiu
309 #define LONG_SUBU subu
314 #define LONG_SLLV sllv
316 #define LONG_SRLV srlv
318 #define LONG_SRAV srav
326 #if (_MIPS_SZLONG == 64)
327 #define LONG_ADD dadd
328 #define LONG_ADDU daddu
329 #define LONG_ADDI daddi
330 #define LONG_ADDIU daddiu
331 #define LONG_SUB dsub
332 #define LONG_SUBU dsubu
336 #define LONG_SLL dsll
337 #define LONG_SLLV dsllv
338 #define LONG_SRL dsrl
339 #define LONG_SRLV dsrlv
340 #define LONG_SRA dsra
341 #define LONG_SRAV dsrav
350 * How to add/sub/load/store/shift pointers.
352 #if (_MIPS_SZPTR == 32)
354 #define PTR_ADDU addu
355 #define PTR_ADDI addi
356 #define PTR_ADDIU addiu
358 #define PTR_SUBU subu
364 #define PTR_SLLV sllv
366 #define PTR_SRLV srlv
368 #define PTR_SRAV srav
370 #define PTR_SCALESHIFT 2
377 #if (_MIPS_SZPTR == 64)
379 #define PTR_ADDU daddu
380 #define PTR_ADDI daddi
381 #define PTR_ADDIU daddiu
383 #define PTR_SUBU dsubu
389 #define PTR_SLLV dsllv
391 #define PTR_SRLV dsrlv
393 #define PTR_SRAV dsrav
395 #define PTR_SCALESHIFT 3
403 * Some cp0 registers were extended to 64bit for MIPS III.
405 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
409 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
414 #define SSNOP sll zero, zero, 1
416 #ifdef CONFIG_SGI_IP28
417 /* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
418 #include <asm/cacheops.h>
419 #define R10KCBARRIER(addr) cache CACHE_BARRIER, addr;
421 #define R10KCBARRIER(addr)
424 #endif /* __ASM_ASM_H */