arch/mips/dts/serval2_pcb112.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2018 Microsemi Corporation
   4  */
   5
   6 /dts-v1/;
   7 #include "mscc,jr2.dtsi"
   8 #include <dt-bindings/mscc/jr2_data.h>
   9
  10 / {
  11         model = "Serval2 NID PCB112 Reference Board";
  12         compatible = "mscc,serval2-pcb110", "mscc,jr2";
  13
  14         aliases {
  15                 spi0 = &spi0;
  16                 serial0 = &uart0;
  17         };
  18
  19         chosen {
  20                 stdout-path = "serial0:115200n8";
  21         };
  22
  23         gpio-leds {
  24                 compatible = "gpio-leds";
  25
  26                 status_green {
  27                         label = "pcb110:green:status";
  28                         gpios = <&gpio 12 0>;
  29                         default-state = "on";
  30                 };
  31
  32                 status_red {
  33                         label = "pcb110:red:status";
  34                         gpios = <&gpio 13 0>;
  35                         default-state = "off";
  36                 };
  37         };
  38 };
  39
  40 &uart0 {
  41         status = "okay";
  42 };
  43
  44 &spi0 {
  45         status = "okay";
  46         spi-flash@0 {
  47                 compatible = "jedec,spi-nor";
  48                 spi-max-frequency = <18000000>; /* input clock */
  49                 reg = <0>; /* CS0 */
  50         };
  51 };
  52
  53 &sgpio {
  54         status = "okay";
  55         sgpio-ports = <0x0000ffff>;
  56 };
  57
  58 &sgpio2 {
  59         status = "okay";
  60         sgpio-ports = <0x3fe0ffff>;
  61 };
  62
  63 &mdio0 {
  64         status = "okay";
  65
  66         phy16: ethernet-phy@16 {
  67                 reg = <16>;
  68         };
  69         phy17: ethernet-phy@17 {
  70                 reg = <17>;
  71         };
  72         phy18: ethernet-phy@18 {
  73                 reg = <18>;
  74         };
  75         phy19: ethernet-phy@19 {
  76                 reg = <19>;
  77         };
  78 };
  79
  80 &switch {
  81         ethernet-ports {
  82
  83                 port0: port@0 {
  84                         reg = <24>;
  85                         phy-handle = <&phy16>;
  86                         phys = <&serdes_hsio 24 SERDES6G(0) PHY_MODE_SGMII>;
  87                 };
  88                 port1: port@1 {
  89                         reg = <25>;
  90                         phy-handle = <&phy17>;
  91                         phys = <&serdes_hsio 25 SERDES6G(1) PHY_MODE_SGMII>;
  92                 };
  93                 port2: port@2 {
  94                         reg = <26>;
  95                         phy-handle = <&phy18>;
  96                         phys = <&serdes_hsio 26 SERDES6G(2) PHY_MODE_SGMII>;
  97                 };
  98                 port3: port@3 {
  99                         reg = <27>;
 100                         phy-handle = <&phy19>;
 101                         phys = <&serdes_hsio 27 SERDES6G(3) PHY_MODE_SGMII>;
 102                 };
 103         };
 104 };