arch/mips/dts/ocelot_pcb120.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2018 Microsemi Corporation
   4  */
   5
   6 /dts-v1/;
   7 #include "mscc,ocelot_pcb.dtsi"
   8 #include <dt-bindings/mscc/ocelot_data.h>
   9
  10 / {
  11         model = "Ocelot PCB120 Reference Board";
  12         compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
  13
  14         chosen {
  15                 stdout-path = "serial0:115200n8";
  16         };
  17
  18         gpio-leds {
  19                 compatible = "gpio-leds";
  20
  21                 poe_green {
  22                         label = "pcb120:green:poe";
  23                         gpios = <&sgpio 44 1>; /* p12.1 */
  24                         default-state = "off";
  25                 };
  26
  27                 poe_red {
  28                         label = "pcb120:red:poe";
  29                         gpios = <&sgpio 12 1>; /* p12.0 */
  30                         default-state = "off";
  31                 };
  32
  33                 alarm_green {
  34                         label = "pcb120:green:alarm";
  35                         gpios = <&sgpio 45 1>; /* p13.1 */
  36                         default-state = "off";
  37                 };
  38
  39                 alarm_red {
  40                         label = "pcb120:red:alarm";
  41                         gpios = <&sgpio 13 1>; /* p13.0 */
  42                         default-state = "off";
  43                 };
  44
  45                 dc_a_green {
  46                         label = "pcb120:green:dc_a";
  47                         gpios = <&sgpio 46 1>; /* p14.1 */
  48                         default-state = "off";
  49                 };
  50
  51                 dc_a_red {
  52                         label = "pcb120:red:dc_a";
  53                         gpios = <&sgpio 14 1>; /* p14.0 */
  54                         default-state = "off";
  55                 };
  56
  57                 dc_b_green {
  58                         label = "pcb120:green:dc_b";
  59                         gpios = <&sgpio 47 1>; /* p15.1 */
  60                         default-state = "off";
  61                 };
  62
  63                 dc_b_red {
  64                         label = "pcb120:red:dc_b";
  65                         gpios = <&sgpio 15 1>; /* p15.0 */
  66                         default-state = "off";
  67                 };
  68
  69                 status_green {
  70                         label = "pcb120:green:status";
  71                         gpios = <&sgpio 48 1>; /* p16.1 */
  72                         default-state = "on";
  73                 };
  74
  75                 status_red {
  76                         label = "pcb120:red:alarm";
  77                         gpios = <&sgpio 16 1>; /* p16.0 */
  78                         default-state = "off";
  79                 };
  80
  81         };
  82
  83 };
  84
  85 &sgpio {
  86         status = "okay";
  87         mscc,sgpio-ports = <0x000FFFFF>;
  88 };
  89
  90 &mdio0 {
  91         status = "okay";
  92
  93         phy4: ethernet-phy@4 {
  94                 reg = <3>;
  95         };
  96         phy5: ethernet-phy@5 {
  97                 reg = <2>;
  98         };
  99         phy6: ethernet-phy@6 {
 100                 reg = <1>;
 101         };
 102         phy7: ethernet-phy@7 {
 103                 reg = <0>;
 104         };
 105 };
 106
 107 &mdio1 {
 108         status = "okay";
 109
 110         phy0: ethernet-phy@0 {
 111                 reg = <3>;
 112         };
 113         phy1: ethernet-phy@1 {
 114                 reg = <2>;
 115         };
 116         phy2: ethernet-phy@2 {
 117                 reg = <1>;
 118         };
 119         phy3: ethernet-phy@3 {
 120                 reg = <0>;
 121         };
 122 };
 123
 124 &switch {
 125         ethernet-ports {
 126                 port0: port@0 {
 127                         reg = <5>;
 128                         phy-handle = <&phy0>;
 129                         phys = <&serdes_hsio 5 SERDES1G(2) PHY_MODE_SGMII>;
 130                 };
 131                 port1: port@1 {
 132                         reg = <9>;
 133                         phy-handle = <&phy1>;
 134                         phys = <&serdes_hsio 9 SERDES1G(3) PHY_MODE_SGMII>;
 135                 };
 136                 port2: port@2 {
 137                         reg = <6>;
 138                         phy-handle = <&phy2>;
 139                         phys = <&serdes_hsio 6 SERDES1G(4) PHY_MODE_SGMII>;
 140                 };
 141                 port3: port@3 {
 142                         reg = <4>;
 143                         phy-handle = <&phy3>;
 144                         phys = <&serdes_hsio 4 SERDES1G(5) PHY_MODE_SGMII>;
 145                 };
 146                 port4: port@4 {
 147                         reg = <3>;
 148                         phy-handle = <&phy4>;
 149                 };
 150                 port5: port@5 {
 151                         reg = <2>;
 152                         phy-handle = <&phy5>;
 153                 };
 154                 port6: port@6 {
 155                         reg = <1>;
 156                         phy-handle = <&phy6>;
 157                 };
 158                 port7: port@7 {
 159                         reg = <0>;
 160                         phy-handle = <&phy7>;
 161                 };
 162         };
 163 };