arch/mips/dts/nexys4ddr.dts

   1 /dts-v1/;
   2
   3 #include "microAptiv.dtsi"
   4
   5 / {
   6         compatible = "digilent,nexys4ddr";
   7
   8         memory {
   9                 device_type = "memory";
  10                 reg = <0x0 0x08000000>;
  11         };
  12
  13         cpuintc: interrupt-controller@0 {
  14                 #address-cells = <0>;
  15                 #interrupt-cells = <1>;
  16                 interrupt-controller;
  17                 compatible = "mti,cpu-interrupt-controller";
  18         };
  19
  20         aliases {
  21                 console = &axi_uart16550;
  22         };
  23
  24         axi_ethernetlite: ethernet@10e00000 {
  25                 compatible = "xlnx,xps-ethernetlite-1.00.a";
  26                 device_type = "network";
  27                 local-mac-address = [08 86 4C 0D F7 09];
  28                 phy-handle = <&phy0>;
  29                 reg = <0x10e00000 0x10000>;
  30                 xlnx,duplex = <0x1>;
  31                 xlnx,include-global-buffers = <0x1>;
  32                 xlnx,include-internal-loopback = <0x0>;
  33                 xlnx,include-mdio = <0x1>;
  34                 xlnx,instance = "axi_ethernetlite_inst";
  35                 xlnx,rx-ping-pong = <0x1>;
  36                 xlnx,s-axi-id-width = <0x1>;
  37                 xlnx,tx-ping-pong = <0x1>;
  38                 xlnx,use-internal = <0x0>;
  39                 mdio {
  40                         #address-cells = <1>;
  41                         #size-cells = <0>;
  42                         phy0: phy@1 {
  43                                 compatible = <0x0007c0f0 0xfffffff0>;
  44                                 device_type = "ethernet-phy";
  45                                 reg = <1>;
  46                         } ;
  47                 } ;
  48         } ;
  49
  50
  51         axi_uart16550: serial@10400000 {
  52                 compatible = "ns16550a";
  53                 reg = <0x10400000 0x10000>;
  54
  55                 reg-shift = <2>;
  56                 reg-offset = <0x1000>;
  57
  58                 clock-frequency = <50000000>;
  59
  60         };
  61 };
  62