arch/mips/dts/mscc,servalt.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2018 Microsemi Corporation
   4  */
   5
   6 / {
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         compatible = "mscc,servalt";
  10
  11         cpus {
  12                 #address-cells = <1>;
  13                 #size-cells = <0>;
  14
  15                 cpu@0 {
  16                         compatible = "mips,mips24KEc";
  17                         device_type = "cpu";
  18                         clocks = <&cpu_clk>;
  19                         reg = <0>;
  20                 };
  21         };
  22
  23         aliases {
  24                 serial0 = &uart0;
  25         };
  26
  27         cpuintc: interrupt-controller@0 {
  28                 #address-cells = <0>;
  29                 #interrupt-cells = <1>;
  30                 interrupt-controller;
  31                 compatible = "mti,cpu-interrupt-controller";
  32         };
  33
  34         cpu_clk: cpu-clock {
  35                 compatible = "fixed-clock";
  36                 #clock-cells = <0>;
  37                 clock-frequency = <500000000>;
  38         };
  39
  40         sys_clk: sys-clk {
  41                 compatible = "fixed-clock";
  42                 #clock-cells = <0>;
  43                 clock-frequency = <250000000>;
  44         };
  45
  46         ahb_clk: ahb-clk {
  47                 compatible = "fixed-clock";
  48                 #clock-cells = <0>;
  49                 clock-frequency = <250000000>;
  50         };
  51
  52         ahb {
  53                 compatible = "simple-bus";
  54                 #address-cells = <1>;
  55                 #size-cells = <1>;
  56                 ranges = <0 0x70000000 0x2000000>;
  57
  58                 interrupt-parent = <&intc>;
  59
  60                 cpu_ctrl: syscon@0 {
  61                         compatible = "mscc,servalt-cpu-syscon", "syscon";
  62                         reg = <0x0 0x2c>;
  63                 };
  64
  65                 intc: interrupt-controller@70 {
  66                         compatible = "mscc,servalt-icpu-intr";
  67                         reg = <0x70 0x74>;
  68                         #interrupt-cells = <1>;
  69                         interrupt-controller;
  70                         interrupt-parent = <&cpuintc>;
  71                         interrupts = <2>;
  72                 };
  73
  74                 uart0: serial@100000 {
  75                         pinctrl-0 = <&uart_pins>;
  76                         pinctrl-names = "default";
  77                         compatible = "ns16550a";
  78                         reg = <0x100000 0x20>;
  79                         interrupts = <6>;
  80                         clocks = <&ahb_clk>;
  81                         reg-io-width = <4>;
  82                         reg-shift = <2>;
  83
  84                         status = "disabled";
  85                 };
  86
  87                 uart2: serial@100800 {
  88                         pinctrl-0 = <&uart2_pins>;
  89                         pinctrl-names = "default";
  90                         compatible = "ns16550a";
  91                         reg = <0x100800 0x20>;
  92                         interrupts = <7>;
  93                         clocks = <&ahb_clk>;
  94                         reg-io-width = <4>;
  95                         reg-shift = <2>;
  96
  97                         status = "disabled";
  98                 };
  99
 100                 reset@1010008 {
 101                         compatible = "mscc,servalt-chip-reset";
 102                         reg = <0x1010008 0x4>;
 103                 };
 104
 105                 gpio: pinctrl@1010034 {
 106                         compatible = "mscc,servalt-pinctrl";
 107                         reg = <0x1010034 0x90>;
 108                         gpio-controller;
 109                         #gpio-cells = <2>;
 110                         gpio-ranges = <&gpio 0 0 36>;
 111
 112                         sgpio_pins: sgpio-pins {
 113                                 pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
 114                                 function = "sio";
 115                         };
 116
 117                         uart_pins: uart-pins {
 118                                 pins = "GPIO_6", "GPIO_7";
 119                                 function = "uart";
 120                         };
 121
 122                         uart2_pins: uart2-pins {
 123                                 pins = "GPIO_20", "GPIO_21";
 124                                 function = "uart2";
 125                         };
 126                 };
 127
 128                 spi0: spi-bitbang {
 129                         compatible = "mscc,luton-bb-spi";
 130                         status = "okay";
 131                         reg = <0x50 0x4>;
 132                         num-chipselects = <1>;
 133                         #address-cells = <1>;
 134                         #size-cells = <0>;
 135                 };
 136
 137                 sgpio: gpio@1010120 {
 138                         compatible = "mscc,ocelot-sgpio";
 139                         status = "disabled";
 140                         clocks = <&sys_clk>;
 141                         pinctrl-0 = <&sgpio_pins>;
 142                         pinctrl-names = "default";
 143                         reg = <0x1010120 0x100>;
 144                         gpio-controller;
 145                         #gpio-cells = <2>;
 146                         gpio-ranges = <&sgpio 0 0 128>;
 147                 };
 148
 149                 switch: switch@1010000 {
 150                         compatible = "mscc,vsc7437-switch";
 151                         reg = <0x01030000 0x0100>,   // VTSS_TO_DEV_0
 152                               <0x01040000 0x0100>,   // VTSS_TO_DEV_1
 153                               <0x01f00000 0x100000>, // ANA_AC
 154                               <0x01d00000 0x100000>, // ANA_CL
 155                               <0x01e00000 0x100000>, // ANA_L2
 156                               <0x01120000 0x10000>,  // ASM
 157                               <0x01130000 0x00000>,  // LRN
 158                               <0x017d0000 0x10000>,  // QFWD
 159                               <0x01020000 0x20000>,  // QS
 160                               <0x017e0000 0x10000>,  // QSYS
 161                               <0x01b00000 0x80000>;  // REW
 162                         reg-names = "port0", "port1",
 163                                     "ana_ac", "ana_cl", "ana_l2", "asm", "lrn",
 164                                     "qfwd", "qs", "qsys", "rew";
 165                         status = "okay";
 166
 167                         ethernet-ports {
 168                                 #address-cells = <1>;
 169                                 #size-cells = <0>;
 170                         };
 171                 };
 172
 173                 mdio0: mdio@010100c4 {
 174                         #address-cells = <1>;
 175                         #size-cells = <0>;
 176                         compatible = "mscc,jr2-miim";
 177                         reg = <0x010100c4 0x24>;
 178                         status = "disabled";
 179                 };
 180
 181                 mdio1: mdio@010100e8 {
 182                         #address-cells = <1>;
 183                         #size-cells = <0>;
 184                         compatible = "mscc,jr2-miim";
 185                         reg = <0x010100e8 0x24>;
 186                         status = "disabled";
 187                 };
 188         };
 189 };