arch/mips/dts/jr2_pcb110.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2018 Microsemi Corporation
   4  */
   5
   6 /dts-v1/;
   7 #include "mscc,jr2.dtsi"
   8 #include <dt-bindings/mscc/jr2_data.h>
   9
  10 / {
  11         model = "Jaguar2 Cu8-Sfp16 PCB110 Reference Board";
  12         compatible = "mscc,jr2-pcb110", "mscc,jr2";
  13
  14         aliases {
  15                 spi0 = &spi0;
  16                 serial0 = &uart0;
  17         };
  18
  19         chosen {
  20                 stdout-path = "serial0:115200n8";
  21         };
  22
  23         gpio-leds {
  24                 compatible = "gpio-leds";
  25
  26                 status_green {
  27                         label = "pcb110:green:status";
  28                         gpios = <&gpio 12 0>;
  29                         default-state = "on";
  30                 };
  31
  32                 status_red {
  33                         label = "pcb110:red:status";
  34                         gpios = <&gpio 13 0>;
  35                         default-state = "off";
  36                 };
  37         };
  38 };
  39
  40 &uart0 {
  41         status = "okay";
  42 };
  43
  44 &spi0 {
  45         status = "okay";
  46         spi-flash@0 {
  47                 compatible = "jedec,spi-nor";
  48                 spi-max-frequency = <18000000>; /* input clock */
  49                 reg = <0>; /* CS0 */
  50         };
  51 };
  52
  53 &gpio {
  54         /* SPIO only use DO, CLK, no inputs */
  55         sgpio1_pins: sgpio1-pins {
  56                 pins = "GPIO_4", "GPIO_5";
  57                 function = "sg1";
  58         };
  59 };
  60
  61 &sgpio {
  62         status = "okay";
  63         sgpio-ports = <0x00ffffff>;
  64 };
  65
  66 &sgpio1 {
  67         status = "okay";
  68         sgpio-ports = <0x00ff0000>;
  69 };
  70
  71 &sgpio2 {
  72         status = "okay";
  73         sgpio-ports = <0x3f00ffff>;
  74         gpio-ranges = <&sgpio2 0 0 96>;
  75 };
  76
  77 &mdio1 {
  78         status = "okay";
  79
  80         phy0: ethernet-phy@0 {
  81                 reg = <0>;
  82         };
  83         phy1: ethernet-phy@1 {
  84                 reg = <1>;
  85         };
  86         phy2: ethernet-phy@2 {
  87                 reg = <2>;
  88         };
  89         phy3: ethernet-phy@3 {
  90                 reg = <3>;
  91         };
  92         phy4: ethernet-phy@4 {
  93                 reg = <4>;
  94         };
  95         phy5: ethernet-phy@5 {
  96                 reg = <5>;
  97         };
  98         phy6: ethernet-phy@6 {
  99                 reg = <6>;
 100         };
 101         phy7: ethernet-phy@7 {
 102                 reg = <7>;
 103         };
 104 };
 105
 106 &switch {
 107         ethernet-ports {
 108
 109                 port0: port@0 {
 110                         reg = <0>;
 111                         phy-handle = <&phy0>;
 112                         phys = <&serdes_hsio 0 SERDES1G(1) PHY_MODE_SGMII>;
 113                 };
 114                 port1: port@1 {
 115                         reg = <1>;
 116                         phy-handle = <&phy1>;
 117                         phys = <&serdes_hsio 1 SERDES1G(2) PHY_MODE_SGMII>;
 118                 };
 119                 port2: port@2 {
 120                         reg = <2>;
 121                         phy-handle = <&phy2>;
 122                         phys = <&serdes_hsio 2 SERDES1G(3) PHY_MODE_SGMII>;
 123                 };
 124                 port3: port@3 {
 125                         reg = <3>;
 126                         phy-handle = <&phy3>;
 127                         phys = <&serdes_hsio 3 SERDES1G(4) PHY_MODE_SGMII>;
 128                 };
 129                 port4: port@4 {
 130                         reg = <4>;
 131                         phy-handle = <&phy4>;
 132                         phys = <&serdes_hsio 4 SERDES1G(5) PHY_MODE_SGMII>;
 133                 };
 134                 port5: port@5 {
 135                         reg = <5>;
 136                         phy-handle = <&phy5>;
 137                         phys = <&serdes_hsio 5 SERDES1G(6) PHY_MODE_SGMII>;
 138                 };
 139                 port6: port@6 {
 140                         reg = <6>;
 141                         phy-handle = <&phy6>;
 142                         phys = <&serdes_hsio 6 SERDES1G(7) PHY_MODE_SGMII>;
 143                 };
 144                 port7: port@7 {
 145                         reg = <7>;
 146                         phy-handle = <&phy7>;
 147                         phys = <&serdes_hsio 7 SERDES1G(8) PHY_MODE_SGMII>;
 148                 };
 149         };
 150 };