2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/clock/bcm6358-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/bcm6358-reset.h>
10 #include "skeleton.dtsi"
13 compatible = "brcm,bcm6358";
16 reg = <0xfffe0000 0x4>;
22 compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
29 compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
37 compatible = "simple-bus";
42 periph_osc: periph-osc {
43 compatible = "fixed-clock";
45 clock-frequency = <50000000>;
49 periph_clk: periph-clk {
50 compatible = "brcm,bcm6345-clk";
51 reg = <0xfffe0004 0x4>;
56 pflash: nor@1e000000 {
57 compatible = "cfi-flash";
58 reg = <0x1e000000 0x2000000>;
67 compatible = "simple-bus";
72 pll_cntl: syscon@fffe0008 {
73 compatible = "syscon";
74 reg = <0xfffe0008 0x4>;
78 compatible = "syscon-reboot";
84 periph_rst: reset-controller@fffe0034 {
85 compatible = "brcm,bcm6345-reset";
86 reg = <0xfffe0034 0x4>;
90 wdt: watchdog@fffe005c {
91 compatible = "brcm,bcm6345-wdt";
92 reg = <0xfffe005c 0xc>;
93 clocks = <&periph_osc>;
97 compatible = "wdt-reboot";
101 gpio1: gpio-controller@fffe0080 {
102 compatible = "brcm,bcm6345-gpio";
103 reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>;
111 gpio0: gpio-controller@fffe0084 {
112 compatible = "brcm,bcm6345-gpio";
113 reg = <0xfffe0084 0x4>, <0xfffe008c 0x4>;
120 leds: led-controller@fffe00d0 {
121 compatible = "brcm,bcm6358-leds";
122 reg = <0xfffe00d0 0x8>;
123 #address-cells = <1>;
129 uart0: serial@fffe0100 {
130 compatible = "brcm,bcm6345-uart";
131 reg = <0xfffe0100 0x18>;
132 clocks = <&periph_osc>;
137 uart1: serial@fffe0120 {
138 compatible = "brcm,bcm6345-uart";
139 reg = <0xfffe0120 0x18>;
140 clocks = <&periph_osc>;
145 memory-controller@fffe1200 {
146 compatible = "brcm,bcm6358-mc";
147 reg = <0xfffe1200 0x4c>;