arch/mips/dts/brcm,bcm6358.dtsi

   1 /*
   2  * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <dt-bindings/clock/bcm6358-clock.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include "skeleton.dtsi"
  10
  11 / {
  12         compatible = "brcm,bcm6358";
  13
  14         cpus {
  15                 reg = <0xfffe0000 0x4>;
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18                 u-boot,dm-pre-reloc;
  19
  20                 cpu@0 {
  21                         compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
  22                         device_type = "cpu";
  23                         reg = <0>;
  24                         u-boot,dm-pre-reloc;
  25                 };
  26
  27                 cpu@1 {
  28                         compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
  29                         device_type = "cpu";
  30                         reg = <1>;
  31                         u-boot,dm-pre-reloc;
  32                 };
  33         };
  34
  35         clocks {
  36                 compatible = "simple-bus";
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 u-boot,dm-pre-reloc;
  40
  41                 periph_osc: periph-osc {
  42                         compatible = "fixed-clock";
  43                         #clock-cells = <0>;
  44                         clock-frequency = <50000000>;
  45                         u-boot,dm-pre-reloc;
  46                 };
  47
  48                 periph_clk: periph-clk {
  49                         compatible = "brcm,bcm6345-clk";
  50                         reg = <0xfffe0004 0x4>;
  51                         #clock-cells = <1>;
  52                 };
  53         };
  54
  55         pflash: nor@1e000000 {
  56                 compatible = "cfi-flash";
  57                 reg = <0x1e000000 0x2000000>;
  58                 bank-width = <2>;
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61
  62                 status = "disabled";
  63         };
  64
  65         ubus {
  66                 compatible = "simple-bus";
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 u-boot,dm-pre-reloc;
  70
  71                 pll_cntl: syscon@fffe0008 {
  72                         compatible = "syscon";
  73                         reg = <0xfffe0008 0x4>;
  74                 };
  75
  76                 syscon-reboot {
  77                         compatible = "syscon-reboot";
  78                         regmap = <&pll_cntl>;
  79                         offset = <0x0>;
  80                         mask = <0x1>;
  81                 };
  82
  83                 gpio1: gpio-controller@fffe0080 {
  84                         compatible = "brcm,bcm6345-gpio";
  85                         reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>;
  86                         gpio-controller;
  87                         #gpio-cells = <2>;
  88                         ngpios = <8>;
  89
  90                         status = "disabled";
  91                 };
  92
  93                 gpio0: gpio-controller@fffe0084 {
  94                         compatible = "brcm,bcm6345-gpio";
  95                         reg = <0xfffe0084 0x4>, <0xfffe008c 0x4>;
  96                         gpio-controller;
  97                         #gpio-cells = <2>;
  98
  99                         status = "disabled";
 100                 };
 101
 102                 leds: led-controller@fffe00d0 {
 103                         compatible = "brcm,bcm6358-leds";
 104                         reg = <0xfffe00d0 0x8>;
 105                         #address-cells = <1>;
 106                         #size-cells = <0>;
 107
 108                         status = "disabled";
 109                 };
 110
 111                 uart0: serial@fffe0100 {
 112                         compatible = "brcm,bcm6345-uart";
 113                         reg = <0xfffe0100 0x18>;
 114                         clocks = <&periph_osc>;
 115
 116                         status = "disabled";
 117                 };
 118
 119                 uart1: serial@fffe0120 {
 120                         compatible = "brcm,bcm6345-uart";
 121                         reg = <0xfffe0120 0x18>;
 122                         clocks = <&periph_osc>;
 123
 124                         status = "disabled";
 125                 };
 126
 127                 memory-controller@fffe1200 {
 128                         compatible = "brcm,bcm6358-mc";
 129                         reg = <0xfffe1200 0x1000>;
 130                         u-boot,dm-pre-reloc;
 131                 };
 132         };
 133 };