arch/mips/dts/brcm,bcm6348.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
   4  */
   5
   6 #include <dt-bindings/clock/bcm6348-clock.h>
   7 #include <dt-bindings/dma/bcm6348-dma.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/reset/bcm6348-reset.h>
  10 #include "skeleton.dtsi"
  11
  12 / {
  13         compatible = "brcm,bcm6348";
  14
  15         aliases {
  16                 spi0 = &spi;
  17         };
  18
  19         cpus {
  20                 reg = <0xfffe0000 0x4>;
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23                 u-boot,dm-pre-reloc;
  24
  25                 cpu@0 {
  26                         compatible = "brcm,bcm6348-cpu", "mips,mips4Kc";
  27                         device_type = "cpu";
  28                         reg = <0>;
  29                         u-boot,dm-pre-reloc;
  30                 };
  31         };
  32
  33         clocks {
  34                 compatible = "simple-bus";
  35                 #address-cells = <1>;
  36                 #size-cells = <1>;
  37                 u-boot,dm-pre-reloc;
  38
  39                 periph_osc: periph-osc {
  40                         compatible = "fixed-clock";
  41                         #clock-cells = <0>;
  42                         clock-frequency = <50000000>;
  43                         u-boot,dm-pre-reloc;
  44                 };
  45
  46                 periph_clk: periph-clk {
  47                         compatible = "brcm,bcm6345-clk";
  48                         reg = <0xfffe0004 0x4>;
  49                         #clock-cells = <1>;
  50                 };
  51         };
  52
  53         pflash: nor@1fc00000 {
  54                 compatible = "cfi-flash";
  55                 reg = <0x1fc00000 0x2000000>;
  56                 bank-width = <2>;
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59
  60                 status = "disabled";
  61         };
  62
  63         ubus {
  64                 compatible = "simple-bus";
  65                 #address-cells = <1>;
  66                 #size-cells = <1>;
  67                 u-boot,dm-pre-reloc;
  68
  69                 pll_cntl: syscon@fffe0008 {
  70                         compatible = "syscon";
  71                         reg = <0xfffe0008 0x4>;
  72                 };
  73
  74                 syscon-reboot {
  75                         compatible = "syscon-reboot";
  76                         regmap = <&pll_cntl>;
  77                         offset = <0x0>;
  78                         mask = <0x1>;
  79                 };
  80
  81                 periph_rst: reset-controller@fffe0028 {
  82                         compatible = "brcm,bcm6345-reset";
  83                         reg = <0xfffe0028 0x4>;
  84                         #reset-cells = <1>;
  85                 };
  86
  87                 wdt: watchdog@fffe021c {
  88                         compatible = "brcm,bcm6345-wdt";
  89                         reg = <0xfffe021c 0xc>;
  90                         clocks = <&periph_osc>;
  91                 };
  92
  93                 wdt-reboot {
  94                         compatible = "wdt-reboot";
  95                         wdt = <&wdt>;
  96                 };
  97
  98                 uart0: serial@fffe0300 {
  99                         compatible = "brcm,bcm6345-uart";
 100                         reg = <0xfffe0300 0x18>;
 101                         clocks = <&periph_osc>;
 102
 103                         status = "disabled";
 104                 };
 105
 106                 gpio1: gpio-controller@fffe0400 {
 107                         compatible = "brcm,bcm6345-gpio";
 108                         reg = <0xfffe0400 0x4>, <0xfffe0408 0x4>;
 109                         gpio-controller;
 110                         #gpio-cells = <2>;
 111                         ngpios = <5>;
 112
 113                         status = "disabled";
 114                 };
 115
 116                 gpio0: gpio-controller@fffe0404 {
 117                         compatible = "brcm,bcm6345-gpio";
 118                         reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
 119                         gpio-controller;
 120                         #gpio-cells = <2>;
 121
 122                         status = "disabled";
 123                 };
 124
 125                 spi: spi@fffe0c00 {
 126                         compatible = "brcm,bcm6348-spi";
 127                         reg = <0xfffe0c00 0xc0>;
 128                         #address-cells = <1>;
 129                         #size-cells = <0>;
 130                         clocks = <&periph_clk BCM6348_CLK_SPI>;
 131                         resets = <&periph_rst BCM6348_RST_SPI>;
 132                         spi-max-frequency = <20000000>;
 133                         num-cs = <4>;
 134
 135                         status = "disabled";
 136                 };
 137
 138                 ohci: usb-controller@fffe1b00 {
 139                         compatible = "brcm,bcm6348-ohci", "generic-ohci";
 140                         reg = <0xfffe1b00 0x100>;
 141                         phys = <&usbh>;
 142                         big-endian;
 143
 144                         status = "disabled";
 145                 };
 146
 147                 usbh: usb-phy@fffe1c00 {
 148                         compatible = "brcm,bcm6348-usbh";
 149                         reg = <0xfffe1c00 0x4>;
 150                         #phy-cells = <0>;
 151                         clocks = <&periph_clk BCM6348_CLK_USBH>;
 152                         clock-names = "usbh";
 153                         resets = <&periph_rst BCM6348_RST_USBH>;
 154
 155                         status = "disabled";
 156                 };
 157
 158                 memory-controller@fffe2300 {
 159                         compatible = "brcm,bcm6338-mc";
 160                         reg = <0xfffe2300 0x38>;
 161                         u-boot,dm-pre-reloc;
 162                 };
 163
 164                 enet0: ethernet@fffe6000 {
 165                         compatible = "brcm,bcm6348-enet";
 166                         #address-cells = <1>;
 167                         #size-cells = <0>;
 168                         reg = <0xfffe6000 0x2dc>;
 169                         dmas = <&iudma BCM6348_DMA_ENET0_RX>,
 170                                <&iudma BCM6348_DMA_ENET0_TX>;
 171                         dma-names = "rx",
 172                                     "tx";
 173
 174                         status = "disabled";
 175                 };
 176
 177                 enet1: ethernet@fffe6800 {
 178                         compatible = "brcm,bcm6348-enet";
 179                         #address-cells = <1>;
 180                         #size-cells = <0>;
 181                         reg = <0xfffe6800 0x2dc>;
 182                         dmas = <&iudma BCM6348_DMA_ENET1_RX>,
 183                                <&iudma BCM6348_DMA_ENET1_TX>;
 184                         dma-names = "rx",
 185                                     "tx";
 186
 187                         status = "disabled";
 188                 };
 189
 190                 iudma: dma-controller@fffe7000 {
 191                         compatible = "brcm,bcm6348-iudma";
 192                         reg = <0xfffe7000 0x1c>,
 193                               <0xfffe7100 0x40>,
 194                               <0xfffe7200 0x40>;
 195                         reg-names = "dma",
 196                                     "dma-channels",
 197                                     "dma-sram";
 198                         #dma-cells = <1>;
 199                         dma-channels = <4>;
 200                         clocks = <&periph_clk BCM6348_CLK_ENET>;
 201                         resets = <&periph_rst BCM6348_RST_ENET>,
 202                                  <&periph_rst BCM6348_RST_DMAMEM>;
 203                 };
 204         };
 205 };