2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/clock/bcm63268-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/power-domain/bcm63268-power-domain.h>
10 #include <dt-bindings/reset/bcm63268-reset.h>
11 #include "skeleton.dtsi"
14 compatible = "brcm,bcm63268";
22 reg = <0x10000000 0x4>;
28 compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
35 compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
43 compatible = "simple-bus";
48 hsspi_pll: hsspi-pll {
49 compatible = "fixed-clock";
51 clock-frequency = <400000000>;
54 periph_osc: periph-osc {
55 compatible = "fixed-clock";
57 clock-frequency = <50000000>;
61 periph_clk: periph-clk {
62 compatible = "brcm,bcm6345-clk";
63 reg = <0x10000004 0x4>;
67 timer_clk: timer-clk {
68 compatible = "brcm,bcm6345-clk";
69 reg = <0x100000ac 0x4>;
75 compatible = "simple-bus";
80 pll_cntl: syscon@10000008 {
81 compatible = "syscon";
82 reg = <0x10000008 0x4>;
86 compatible = "syscon-reboot";
92 periph_rst: reset-controller@10000010 {
93 compatible = "brcm,bcm6345-reset";
94 reg = <0x10000010 0x4>;
98 wdt: watchdog@1000009c {
99 compatible = "brcm,bcm6345-wdt";
100 reg = <0x1000009c 0xc>;
101 clocks = <&periph_osc>;
105 compatible = "wdt-reboot";
109 gpio1: gpio-controller@100000c0 {
110 compatible = "brcm,bcm6345-gpio";
111 reg = <0x100000c0 0x4>, <0x100000c8 0x4>;
119 gpio0: gpio-controller@100000c4 {
120 compatible = "brcm,bcm6345-gpio";
121 reg = <0x100000c4 0x4>, <0x100000cc 0x4>;
128 uart0: serial@10000180 {
129 compatible = "brcm,bcm6345-uart";
130 reg = <0x10000180 0x18>;
131 clocks = <&periph_osc>;
136 uart1: serial@100001a0 {
137 compatible = "brcm,bcm6345-uart";
138 reg = <0x100001a0 0x18>;
139 clocks = <&periph_osc>;
144 periph_pwr: power-controller@1000184c {
145 compatible = "brcm,bcm6328-power-domain";
146 reg = <0x1000184c 0x4>;
147 #power-domain-cells = <1>;
150 lsspi: spi@10000800 {
151 compatible = "brcm,bcm6358-spi";
152 reg = <0x10000800 0x70c>;
153 #address-cells = <1>;
155 clocks = <&periph_clk BCM63268_CLK_SPI>;
156 resets = <&periph_rst BCM63268_RST_SPI>;
157 spi-max-frequency = <20000000>;
163 hsspi: spi@10001000 {
164 compatible = "brcm,bcm6328-hsspi";
165 #address-cells = <1>;
167 reg = <0x10001000 0x600>;
168 clocks = <&periph_clk BCM63268_CLK_HSSPI>, <&hsspi_pll>;
169 clock-names = "hsspi", "pll";
170 resets = <&periph_rst BCM63268_RST_SPI>;
171 spi-max-frequency = <50000000>;
177 leds: led-controller@10001900 {
178 compatible = "brcm,bcm6328-leds";
179 reg = <0x10001900 0x24>;
180 #address-cells = <1>;
186 memory-controller@10003000 {
187 compatible = "brcm,bcm6328-mc";
188 reg = <0x10003000 0x894>;