2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/clock/bcm3380-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/bcm3380-reset.h>
10 #include "skeleton.dtsi"
13 compatible = "brcm,bcm3380";
16 reg = <0x14e00000 0x4>;
22 compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
29 compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
37 compatible = "simple-bus";
42 periph_osc: periph-osc {
43 compatible = "fixed-clock";
45 clock-frequency = <50000000>;
49 periph_clk0: periph-clk@14e00004 {
50 compatible = "brcm,bcm6345-clk";
51 reg = <0x14e00004 0x4>;
55 periph_clk1: periph-clk@14e00008 {
56 compatible = "brcm,bcm6345-clk";
57 reg = <0x14e00008 0x4>;
63 compatible = "simple-bus";
68 memory-controller@12000000 {
69 compatible = "brcm,bcm6328-mc";
70 reg = <0x12000000 0x1000>;
74 periph_rst0: reset-controller@14e0008c {
75 compatible = "brcm,bcm6345-reset";
76 reg = <0x14e0008c 0x4>;
80 periph_rst1: reset-controller@14e00090 {
81 compatible = "brcm,bcm6345-reset";
82 reg = <0x14e00090 0x4>;
86 pll_cntl: syscon@14e00094 {
87 compatible = "syscon";
88 reg = <0x14e00094 0x4>;
92 compatible = "syscon-reboot";
98 wdt: watchdog@14e000dc {
99 compatible = "brcm,bcm6345-wdt";
100 reg = <0x14e000dc 0xc>;
102 clocks = <&periph_osc>;
106 compatible = "wdt-reboot";
110 gpio0: gpio-controller@14e00100 {
111 compatible = "brcm,bcm6345-gpio";
112 reg = <0x14e00100 0x4>, <0x14e00108 0x4>;
119 gpio1: gpio-controller@14e00104 {
120 compatible = "brcm,bcm6345-gpio";
121 reg = <0x14e00104 0x4>, <0x14e0010c 0x4>;
129 uart0: serial@14e00200 {
130 compatible = "brcm,bcm6345-uart";
131 reg = <0x14e00200 0x18>;
132 clocks = <&periph_osc>;
137 uart1: serial@14e00220 {
138 compatible = "brcm,bcm6345-uart";
139 reg = <0x14e00220 0x18>;
140 clocks = <&periph_osc>;
145 leds: led-controller@14e00f00 {
146 compatible = "brcm,bcm6328-leds";
147 reg = <0x14e00f00 0x1c>;
148 #address-cells = <1>;