2 * Startup Code for MIPS32 CPU-core
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm-offsets.h>
27 #include <asm/regdef.h>
28 #include <asm/mipsregs.h>
30 #ifndef CONFIG_SYS_MIPS_CACHE_MODE
31 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
35 * For the moment disable interrupts, mark the kernel mode and
36 * set ST0_KX so that the CPU does not spit fire when using
39 .macro setup_c0_status set clr
42 or t0, ST0_CU0 | \set | 0x1f | \clr
55 /* U-boot entry point */
60 #ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
62 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
63 * access external NOR flashes. If the board boots from NOR flash the
64 * internal BootROM does a blind read at address 0xB0000010 to read the
65 * initial configuration for that EBU in order to access the flash
66 * device with correct parameters. This config option is board-specific.
68 .word CONFIG_SYS_XWAY_EBU_BOOTCFG
73 /* TLB refill, 32 bit task */
78 /* XTLB refill, 64 bit task */
83 /* Cache error exception */
88 /* General exception */
93 /* Catch interrupt exceptions */
98 /* EJTAG debug exception */
105 /* Clear watch registers */
106 mtc0 zero, CP0_WATCHLO
107 mtc0 zero, CP0_WATCHHI
109 /* WP(Watch Pending), SW0/1 should be cleared */
116 mtc0 zero, CP0_COMPARE
118 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
119 /* CONFIG0 register */
120 li t0, CONF_CM_UNCACHED
131 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
132 /* Initialize any external memory */
137 /* Initialize caches... */
138 la t9, mips_cache_reset
142 /* ... and enable them */
143 li t0, CONFIG_SYS_MIPS_CACHE_MODE
147 /* Set up temporary stack */
148 li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
155 * void relocate_code (addr_sp, gd, addr_moni)
157 * This "function" does not return, instead it continues in RAM
158 * after relocating the monitor code.
162 * a2 = destination address
167 move sp, a0 # set new stack pointer
169 move s0, a1 # save gd in s0
170 move s2, a2 # save destination address in s2
172 li t0, CONFIG_SYS_MONITOR_BASE
173 sub s1, s2, t0 # s1 <-- relocation offset
176 lw t2, -12(t3) # t2 <-- uboot_end_data
179 add gp, s1 # adjust gp
182 * t0 = source address
183 * t1 = target address
184 * t2 = source end address
193 /* If caches were enabled, we would have to flush them here. */
194 sub a1, t1, s2 # a1 <-- size
197 move a0, s2 # a0 <-- destination address
199 /* Jump to where we've relocated ourselves */
200 addi t0, s2, in_ram - _start
204 .word _GLOBAL_OFFSET_TABLE_
207 .word num_got_entries
211 * Now we want to update GOT.
213 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
214 * generated by GNU ld. Skip these reserved entries from relocation.
216 lw t3, -4(t0) # t3 <-- num_got_entries
217 lw t4, -16(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
218 add t4, s1 # t4 now holds relocated _G_O_T_
219 addi t4, t4, 8 # skipping first two entries
232 lw t1, -12(t0) # t1 <-- uboot_end_data
233 lw t2, -8(t0) # t2 <-- uboot_end
234 add t1, s1 # adjust pointers
243 move a0, s0 # a0 <-- gd