2 * Startup Code for MIPS32 CPU-core
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm-offsets.h>
11 #include <asm/regdef.h>
12 #include <asm/mipsregs.h>
14 #ifndef CONFIG_SYS_MIPS_CACHE_MODE
15 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
19 * For the moment disable interrupts, mark the kernel mode and
20 * set ST0_KX so that the CPU does not spit fire when using
23 .macro setup_c0_status set clr
26 or t0, ST0_CU0 | \set | 0x1f | \clr
39 /* U-boot entry point */
44 #if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
46 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
47 * access external NOR flashes. If the board boots from NOR flash the
48 * internal BootROM does a blind read at address 0xB0000010 to read the
49 * initial configuration for that EBU in order to access the flash
50 * device with correct parameters. This config option is board-specific.
52 .word CONFIG_SYS_XWAY_EBU_BOOTCFG
54 #elif defined(CONFIG_QEMU_MALTA)
56 * Linux expects the Board ID here.
58 .word 0x00000420 # 0x420 (Malta Board with CoreLV)
63 /* TLB refill, 32 bit task */
68 /* XTLB refill, 64 bit task */
73 /* Cache error exception */
78 /* General exception */
83 /* Catch interrupt exceptions */
88 /* EJTAG debug exception */
95 /* Clear watch registers */
96 mtc0 zero, CP0_WATCHLO
97 mtc0 zero, CP0_WATCHHI
99 /* WP(Watch Pending), SW0/1 should be cleared */
106 mtc0 zero, CP0_COMPARE
108 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
109 /* CONFIG0 register */
110 li t0, CONF_CM_UNCACHED
121 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
122 /* Initialize any external memory */
127 /* Initialize caches... */
128 la t9, mips_cache_reset
132 /* ... and enable them */
133 li t0, CONFIG_SYS_MIPS_CACHE_MODE
137 /* Set up temporary stack */
138 li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
145 * void relocate_code (addr_sp, gd, addr_moni)
147 * This "function" does not return, instead it continues in RAM
148 * after relocating the monitor code.
152 * a2 = destination address
157 move sp, a0 # set new stack pointer
159 move s0, a1 # save gd in s0
160 move s2, a2 # save destination address in s2
162 li t0, CONFIG_SYS_MONITOR_BASE
163 sub s1, s2, t0 # s1 <-- relocation offset
166 lw t2, -12(t3) # t2 <-- __image_copy_end
169 add gp, s1 # adjust gp
172 * t0 = source address
173 * t1 = target address
174 * t2 = source end address
183 /* If caches were enabled, we would have to flush them here. */
184 sub a1, t1, s2 # a1 <-- size
187 move a0, s2 # a0 <-- destination address
189 /* Jump to where we've relocated ourselves */
190 addi t0, s2, in_ram - _start
195 .word __rel_dyn_start
196 .word __image_copy_end
197 .word _GLOBAL_OFFSET_TABLE_
198 .word num_got_entries
202 * Now we want to update GOT.
204 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
205 * generated by GNU ld. Skip these reserved entries from relocation.
207 lw t3, -4(t0) # t3 <-- num_got_entries
208 lw t4, -8(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
209 add t4, s1 # t4 now holds relocated _G_O_T_
210 addi t4, t4, 8 # skipping first two entries
222 /* Update dynamic relocations */
223 lw t1, -16(t0) # t1 <-- __rel_dyn_start
224 lw t2, -20(t0) # t2 <-- __rel_dyn_end
226 b 2f # skip first reserved entry
230 lw t3, -4(t1) # t3 <-- relocation info
233 bnez t3, 2f # skip non R_MIPS_REL32 entries
236 lw t3, -8(t1) # t3 <-- location to fix up in FLASH
238 lw t4, 0(t3) # t4 <-- original pointer
239 add t4, s1 # t4 <-- adjusted pointer
241 add t3, s1 # t3 <-- location to fix up in RAM
246 addi t1, 8 # each rel.dyn entry is 8 bytes
251 * GOT is now relocated. Thus __bss_start and __bss_end can be
252 * accessed directly via $gp.
254 la t1, __bss_start # t1 <-- __bss_start
255 la t2, __bss_end # t2 <-- __bss_end
262 move a0, s0 # a0 <-- gd