3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/mipsregs.h>
12 #include <asm/cacheops.h>
13 #include <asm/reboot.h>
15 #define cache_op(op,addr) \
16 __asm__ __volatile__( \
18 " .set noreorder \n" \
19 " .set mips3\n\t \n" \
23 : "i" (op), "R" (*(unsigned char *)(addr)))
25 void __attribute__((weak)) _machine_restart(void)
29 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
33 fprintf(stderr, "*** reset failed ***\n");
37 void flush_cache(ulong start_addr, ulong size)
39 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
40 unsigned long addr = start_addr & ~(lsize - 1);
41 unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
43 /* aend will be miscalculated when size is zero, so we return here */
48 cache_op(HIT_WRITEBACK_INV_D, addr);
49 cache_op(HIT_INVALIDATE_I, addr);
56 void flush_dcache_range(ulong start_addr, ulong stop)
58 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
59 unsigned long addr = start_addr & ~(lsize - 1);
60 unsigned long aend = (stop - 1) & ~(lsize - 1);
63 cache_op(HIT_WRITEBACK_INV_D, addr);
70 void invalidate_dcache_range(ulong start_addr, ulong stop)
72 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
73 unsigned long addr = start_addr & ~(lsize - 1);
74 unsigned long aend = (stop - 1) & ~(lsize - 1);
77 cache_op(HIT_INVALIDATE_D, addr);
84 void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
86 write_c0_entrylo0(low0);
87 write_c0_pagemask(pagemask);
88 write_c0_entrylo1(low1);
90 write_c0_index(index);
94 int cpu_eth_init(bd_t *bis)
96 #ifdef CONFIG_SOC_AU1X00
97 au1x00_enet_initialize(bis);