arch/mips/boot/dts/ingenic/gcw0.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include "jz4770.dtsi"
   5
   6 / {
   7         compatible = "gcw,zero", "ingenic,jz4770";
   8         model = "GCW Zero";
   9
  10         aliases {
  11                 serial0 = &uart0;
  12                 serial1 = &uart1;
  13                 serial2 = &uart2;
  14                 serial3 = &uart3;
  15         };
  16
  17         chosen {
  18                 stdout-path = "serial2:57600n8";
  19         };
  20
  21         board {
  22                 compatible = "simple-bus";
  23                 #address-cells = <1>;
  24                 #size-cells = <1>;
  25                 ranges;
  26
  27                 otg_phy: otg-phy {
  28                         compatible = "usb-nop-xceiv";
  29                         clocks = <&cgu JZ4770_CLK_OTG_PHY>;
  30                         clock-names = "main_clk";
  31                 };
  32         };
  33 };
  34
  35 &ext {
  36         clock-frequency = <12000000>;
  37 };
  38
  39 &uart2 {
  40         status = "okay";
  41 };
  42
  43 &cgu {
  44         /* Put high-speed peripherals under PLL1, such that we can change the
  45          * PLL0 frequency on demand without having to suspend peripherals.
  46          * We use a rate of 432 MHz, which is the least common multiple of
  47          * 27 MHz (required by TV encoder) and 48 MHz (required by USB host).
  48          */
  49         assigned-clocks =
  50                 <&cgu JZ4770_CLK_PLL1>,
  51                 <&cgu JZ4770_CLK_UHC>;
  52         assigned-clock-parents =
  53                 <0>,
  54                 <&cgu JZ4770_CLK_PLL1>;
  55         assigned-clock-rates =
  56                 <432000000>;
  57 };
  58
  59 &uhc {
  60         /* The WiFi module is connected to the UHC. */
  61         status = "okay";
  62 };