arch/mips/ath79/setup.c

   1 /*
   2  *  Atheros AR71XX/AR724X/AR913X specific setup
   3  *
   4  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
   5  *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   6  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   7  *
   8  *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
   9  *
  10  *  This program is free software; you can redistribute it and/or modify it
  11  *  under the terms of the GNU General Public License version 2 as published
  12  *  by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/bootmem.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/of_fdt.h>
  22
  23 #include <asm/bootinfo.h>
  24 #include <asm/idle.h>
  25 #include <asm/time.h>           /* for mips_hpt_frequency */
  26 #include <asm/reboot.h>         /* for _machine_{restart,halt} */
  27 #include <asm/mips_machine.h>
  28 #include <asm/prom.h>
  29 #include <asm/fw/fw.h>
  30
  31 #include <asm/mach-ath79/ath79.h>
  32 #include <asm/mach-ath79/ar71xx_regs.h>
  33 #include "common.h"
  34 #include "dev-common.h"
  35 #include "machtypes.h"
  36
  37 #define ATH79_SYS_TYPE_LEN      64
  38
  39 #define AR71XX_BASE_FREQ        40000000
  40 #define AR724X_BASE_FREQ        5000000
  41 #define AR913X_BASE_FREQ        5000000
  42
  43 static char ath79_sys_type[ATH79_SYS_TYPE_LEN];
  44
  45 static void ath79_restart(char *command)
  46 {
  47         local_irq_disable();
  48         ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
  49         for (;;)
  50                 if (cpu_wait)
  51                         cpu_wait();
  52 }
  53
  54 static void ath79_halt(void)
  55 {
  56         while (1)
  57                 cpu_wait();
  58 }
  59
  60 static void __init ath79_detect_sys_type(void)
  61 {
  62         char *chip = "????";
  63         u32 id;
  64         u32 major;
  65         u32 minor;
  66         u32 rev = 0;
  67
  68         id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
  69         major = id & REV_ID_MAJOR_MASK;
  70
  71         switch (major) {
  72         case REV_ID_MAJOR_AR71XX:
  73                 minor = id & AR71XX_REV_ID_MINOR_MASK;
  74                 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
  75                 rev &= AR71XX_REV_ID_REVISION_MASK;
  76                 switch (minor) {
  77                 case AR71XX_REV_ID_MINOR_AR7130:
  78                         ath79_soc = ATH79_SOC_AR7130;
  79                         chip = "7130";
  80                         break;
  81
  82                 case AR71XX_REV_ID_MINOR_AR7141:
  83                         ath79_soc = ATH79_SOC_AR7141;
  84                         chip = "7141";
  85                         break;
  86
  87                 case AR71XX_REV_ID_MINOR_AR7161:
  88                         ath79_soc = ATH79_SOC_AR7161;
  89                         chip = "7161";
  90                         break;
  91                 }
  92                 break;
  93
  94         case REV_ID_MAJOR_AR7240:
  95                 ath79_soc = ATH79_SOC_AR7240;
  96                 chip = "7240";
  97                 rev = id & AR724X_REV_ID_REVISION_MASK;
  98                 break;
  99
 100         case REV_ID_MAJOR_AR7241:
 101                 ath79_soc = ATH79_SOC_AR7241;
 102                 chip = "7241";
 103                 rev = id & AR724X_REV_ID_REVISION_MASK;
 104                 break;
 105
 106         case REV_ID_MAJOR_AR7242:
 107                 ath79_soc = ATH79_SOC_AR7242;
 108                 chip = "7242";
 109                 rev = id & AR724X_REV_ID_REVISION_MASK;
 110                 break;
 111
 112         case REV_ID_MAJOR_AR913X:
 113                 minor = id & AR913X_REV_ID_MINOR_MASK;
 114                 rev = id >> AR913X_REV_ID_REVISION_SHIFT;
 115                 rev &= AR913X_REV_ID_REVISION_MASK;
 116                 switch (minor) {
 117                 case AR913X_REV_ID_MINOR_AR9130:
 118                         ath79_soc = ATH79_SOC_AR9130;
 119                         chip = "9130";
 120                         break;
 121
 122                 case AR913X_REV_ID_MINOR_AR9132:
 123                         ath79_soc = ATH79_SOC_AR9132;
 124                         chip = "9132";
 125                         break;
 126                 }
 127                 break;
 128
 129         case REV_ID_MAJOR_AR9330:
 130                 ath79_soc = ATH79_SOC_AR9330;
 131                 chip = "9330";
 132                 rev = id & AR933X_REV_ID_REVISION_MASK;
 133                 break;
 134
 135         case REV_ID_MAJOR_AR9331:
 136                 ath79_soc = ATH79_SOC_AR9331;
 137                 chip = "9331";
 138                 rev = id & AR933X_REV_ID_REVISION_MASK;
 139                 break;
 140
 141         case REV_ID_MAJOR_AR9341:
 142                 ath79_soc = ATH79_SOC_AR9341;
 143                 chip = "9341";
 144                 rev = id & AR934X_REV_ID_REVISION_MASK;
 145                 break;
 146
 147         case REV_ID_MAJOR_AR9342:
 148                 ath79_soc = ATH79_SOC_AR9342;
 149                 chip = "9342";
 150                 rev = id & AR934X_REV_ID_REVISION_MASK;
 151                 break;
 152
 153         case REV_ID_MAJOR_AR9344:
 154                 ath79_soc = ATH79_SOC_AR9344;
 155                 chip = "9344";
 156                 rev = id & AR934X_REV_ID_REVISION_MASK;
 157                 break;
 158
 159         case REV_ID_MAJOR_QCA9556:
 160                 ath79_soc = ATH79_SOC_QCA9556;
 161                 chip = "9556";
 162                 rev = id & QCA955X_REV_ID_REVISION_MASK;
 163                 break;
 164
 165         case REV_ID_MAJOR_QCA9558:
 166                 ath79_soc = ATH79_SOC_QCA9558;
 167                 chip = "9558";
 168                 rev = id & QCA955X_REV_ID_REVISION_MASK;
 169                 break;
 170
 171         default:
 172                 panic("ath79: unknown SoC, id:0x%08x", id);
 173         }
 174
 175         ath79_soc_rev = rev;
 176
 177         if (soc_is_qca955x())
 178                 sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
 179                         chip, rev);
 180         else
 181                 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
 182         pr_info("SoC: %s\n", ath79_sys_type);
 183 }
 184
 185 const char *get_system_type(void)
 186 {
 187         return ath79_sys_type;
 188 }
 189
 190 int get_c0_perfcount_int(void)
 191 {
 192         return ATH79_MISC_IRQ(5);
 193 }
 194 EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
 195
 196 unsigned int get_c0_compare_int(void)
 197 {
 198         return CP0_LEGACY_COMPARE_IRQ;
 199 }
 200
 201 void __init plat_mem_setup(void)
 202 {
 203         unsigned long fdt_start;
 204
 205         set_io_port_base(KSEG1);
 206
 207         /* Get the position of the FDT passed by the bootloader */
 208         fdt_start = fw_getenvl("fdt_start");
 209         if (fdt_start)
 210                 __dt_setup_arch((void *)KSEG0ADDR(fdt_start));
 211 #ifdef CONFIG_BUILTIN_DTB
 212         else
 213                 __dt_setup_arch(__dtb_start);
 214 #endif
 215
 216         ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 217                                            AR71XX_RESET_SIZE);
 218         ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
 219                                          AR71XX_PLL_SIZE);
 220         ath79_detect_sys_type();
 221         ath79_ddr_ctrl_init();
 222
 223         if (mips_machtype != ATH79_MACH_GENERIC_OF)
 224                 detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
 225
 226         _machine_restart = ath79_restart;
 227         _machine_halt = ath79_halt;
 228         pm_power_off = ath79_halt;
 229 }
 230
 231 void __init plat_time_init(void)
 232 {
 233         unsigned long cpu_clk_rate;
 234         unsigned long ahb_clk_rate;
 235         unsigned long ddr_clk_rate;
 236         unsigned long ref_clk_rate;
 237
 238         ath79_clocks_init();
 239
 240         cpu_clk_rate = ath79_get_sys_clk_rate("cpu");
 241         ahb_clk_rate = ath79_get_sys_clk_rate("ahb");
 242         ddr_clk_rate = ath79_get_sys_clk_rate("ddr");
 243         ref_clk_rate = ath79_get_sys_clk_rate("ref");
 244
 245         pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz\n",
 246                 cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000,
 247                 ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000,
 248                 ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000,
 249                 ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000);
 250
 251         mips_hpt_frequency = cpu_clk_rate / 2;
 252 }
 253
 254 static int __init ath79_setup(void)
 255 {
 256         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 257         if  (mips_machtype == ATH79_MACH_GENERIC_OF)
 258                 return 0;
 259
 260         ath79_gpio_init();
 261         ath79_register_uart();
 262         ath79_register_wdt();
 263
 264         mips_machine_setup();
 265
 266         return 0;
 267 }
 268
 269 arch_initcall(ath79_setup);
 270
 271 void __init device_tree_init(void)
 272 {
 273         unflatten_and_copy_device_tree();
 274 }
 275
 276 static void __init ath79_generic_init(void)
 277 {
 278         /* Nothing to do */
 279 }
 280
 281 MIPS_MACHINE(ATH79_MACH_GENERIC,
 282              "Generic",
 283              "Generic AR71XX/AR724X/AR913X based board",
 284              ath79_generic_init);
 285
 286 MIPS_MACHINE(ATH79_MACH_GENERIC_OF,
 287              "DTB",
 288              "Generic AR71XX/AR724X/AR913X based board (DT)",
 289              NULL);