1 menu "MIPS architecture"
8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
12 prompt "Target select"
15 config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
17 select SUPPORTS_BIG_ENDIAN
18 select SUPPORTS_LITTLE_ENDIAN
19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
23 select ROM_EXCEPTION_VECTORS
29 select DYNAMIC_IO_PORT_BASE
34 select SUPPORTS_BIG_ENDIAN
35 select SUPPORTS_LITTLE_ENDIAN
36 select SUPPORTS_CPU_MIPS32_R1
37 select SUPPORTS_CPU_MIPS32_R2
38 select SUPPORTS_CPU_MIPS32_R6
39 select SUPPORTS_CPU_MIPS64_R1
40 select SUPPORTS_CPU_MIPS64_R2
41 select SUPPORTS_CPU_MIPS64_R6
43 select MIPS_L1_CACHE_SHIFT_6
44 select ROM_EXCEPTION_VECTORS
48 select SUPPORTS_BIG_ENDIAN
49 select SUPPORTS_CPU_MIPS32_R1
50 select SUPPORTS_CPU_MIPS32_R2
51 select SYS_MIPS_CACHE_INIT_RAM_LOAD
52 select ROM_EXCEPTION_VECTORS
54 config TARGET_DBAU1X00
55 bool "Support dbau1x00"
56 select SUPPORTS_BIG_ENDIAN
57 select SUPPORTS_LITTLE_ENDIAN
58 select SUPPORTS_CPU_MIPS32_R1
59 select SUPPORTS_CPU_MIPS32_R2
60 select SYS_MIPS_CACHE_INIT_RAM_LOAD
61 select ROM_EXCEPTION_VECTORS
66 select SUPPORTS_LITTLE_ENDIAN
67 select SUPPORTS_CPU_MIPS32_R1
68 select SUPPORTS_CPU_MIPS32_R2
69 select SYS_MIPS_CACHE_INIT_RAM_LOAD
70 select ROM_EXCEPTION_VECTORS
74 bool "Support QCA/Atheros ath79"
79 bool "Support BMIPS SoCs"
88 bool "Support Microchip PIC32"
98 select MIPS_L1_CACHE_SHIFT_6
100 select SUPPORTS_BIG_ENDIAN
101 select SUPPORTS_LITTLE_ENDIAN
102 select SUPPORTS_CPU_MIPS32_R1
103 select SUPPORTS_CPU_MIPS32_R2
104 select SUPPORTS_CPU_MIPS32_R6
105 select SUPPORTS_CPU_MIPS64_R1
106 select SUPPORTS_CPU_MIPS64_R2
107 select SUPPORTS_CPU_MIPS64_R6
108 select ROM_EXCEPTION_VECTORS
110 config TARGET_XILFPGA
111 bool "Support Imagination Xilfpga"
117 select SUPPORTS_LITTLE_ENDIAN
118 select SUPPORTS_CPU_MIPS32_R1
119 select SUPPORTS_CPU_MIPS32_R2
120 select MIPS_L1_CACHE_SHIFT_4
121 select ROM_EXCEPTION_VECTORS
123 This supports IMGTEC MIPSfpga platform
127 source "board/dbau1x00/Kconfig"
128 source "board/imgtec/boston/Kconfig"
129 source "board/imgtec/malta/Kconfig"
130 source "board/imgtec/xilfpga/Kconfig"
131 source "board/micronas/vct/Kconfig"
132 source "board/pb1x00/Kconfig"
133 source "board/qemu-mips/Kconfig"
134 source "arch/mips/mach-ath79/Kconfig"
135 source "arch/mips/mach-bmips/Kconfig"
136 source "arch/mips/mach-pic32/Kconfig"
141 prompt "Endianness selection"
143 Some MIPS boards can be configured for either little or big endian
144 byte order. These modes require different U-Boot images. In general there
145 is one preferred byteorder for a particular system but some systems are
146 just as commonly used in the one or the other endianness.
148 config SYS_BIG_ENDIAN
150 depends on SUPPORTS_BIG_ENDIAN
152 config SYS_LITTLE_ENDIAN
154 depends on SUPPORTS_LITTLE_ENDIAN
159 prompt "CPU selection"
160 default CPU_MIPS32_R2
163 bool "MIPS32 Release 1"
164 depends on SUPPORTS_CPU_MIPS32_R1
167 Choose this option to build an U-Boot for release 1 through 5 of the
171 bool "MIPS32 Release 2"
172 depends on SUPPORTS_CPU_MIPS32_R2
175 Choose this option to build an U-Boot for release 2 through 5 of the
179 bool "MIPS32 Release 6"
180 depends on SUPPORTS_CPU_MIPS32_R6
183 Choose this option to build an U-Boot for release 6 or later of the
187 bool "MIPS64 Release 1"
188 depends on SUPPORTS_CPU_MIPS64_R1
191 Choose this option to build a kernel for release 1 through 5 of the
195 bool "MIPS64 Release 2"
196 depends on SUPPORTS_CPU_MIPS64_R2
199 Choose this option to build a kernel for release 2 through 5 of the
203 bool "MIPS64 Release 6"
204 depends on SUPPORTS_CPU_MIPS64_R6
207 Choose this option to build a kernel for release 6 or later of the
214 config ROM_EXCEPTION_VECTORS
215 bool "Build U-Boot image with exception vectors"
217 Enable this to include exception vectors in the U-Boot image. This is
218 required if the U-Boot entry point is equal to the address of the
219 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
220 U-Boot booted from parallel NOR flash).
221 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
222 In that case the image size will be reduced by 0x500 bytes.
226 menu "OS boot interface"
228 config MIPS_BOOT_CMDLINE_LEGACY
229 bool "Hand over legacy command line to Linux kernel"
232 Enable this option if you want U-Boot to hand over the Yamon-style
233 command line to the kernel. All bootargs will be prepared as argc/argv
234 compatible list. The argument count (argc) is stored in register $a0.
235 The address of the argument list (argv) is stored in register $a1.
237 config MIPS_BOOT_ENV_LEGACY
238 bool "Hand over legacy environment to Linux kernel"
241 Enable this option if you want U-Boot to hand over the Yamon-style
242 environment to the kernel. Information like memory size, initrd
243 address and size will be prepared as zero-terminated key/value list.
244 The address of the environment is stored in register $a2.
247 bool "Hand over a flattened device tree to Linux kernel"
250 Enable this option if you want U-Boot to hand over a flattened
251 device tree to the kernel. According to UHI register $a0 will be set
252 to -2 and the FDT address is stored in $a1.
256 config SUPPORTS_BIG_ENDIAN
259 config SUPPORTS_LITTLE_ENDIAN
262 config SUPPORTS_CPU_MIPS32_R1
265 config SUPPORTS_CPU_MIPS32_R2
268 config SUPPORTS_CPU_MIPS32_R6
271 config SUPPORTS_CPU_MIPS64_R1
274 config SUPPORTS_CPU_MIPS64_R2
277 config SUPPORTS_CPU_MIPS64_R6
282 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
286 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
291 config MIPS_TUNE_14KC
294 config MIPS_TUNE_24KC
297 config MIPS_TUNE_34KC
300 config MIPS_TUNE_74KC
312 config SYS_MIPS_CACHE_INIT_RAM_LOAD
315 config MIPS_INIT_STACK_IN_SRAM
319 Select this if the initial stack frame could be setup in SRAM.
320 Normally the initial stack frame is set up in DRAM which is often
321 only available after lowlevel_init. With this option the initial
322 stack frame and the early C environment is set up before
323 lowlevel_init. Thus lowlevel_init does not need to be implemented
326 config SYS_DCACHE_SIZE
330 The total size of the L1 Dcache, if known at compile time.
332 config SYS_DCACHE_LINE_SIZE
336 The size of L1 Dcache lines, if known at compile time.
338 config SYS_ICACHE_SIZE
342 The total size of the L1 ICache, if known at compile time.
344 config SYS_ICACHE_LINE_SIZE
348 The size of L1 Icache lines, if known at compile time.
350 config SYS_CACHE_SIZE_AUTO
351 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
352 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
354 Select this (or let it be auto-selected by not defining any cache
355 sizes) in order to allow U-Boot to automatically detect the sizes
356 of caches at runtime. This has a small cost in code size & runtime
357 so if you know the cache configuration for your system at compile
358 time it would be beneficial to configure it.
360 config MIPS_L1_CACHE_SHIFT_4
363 config MIPS_L1_CACHE_SHIFT_5
366 config MIPS_L1_CACHE_SHIFT_6
369 config MIPS_L1_CACHE_SHIFT_7
372 config MIPS_L1_CACHE_SHIFT
374 default "7" if MIPS_L1_CACHE_SHIFT_7
375 default "6" if MIPS_L1_CACHE_SHIFT_6
376 default "5" if MIPS_L1_CACHE_SHIFT_5
377 default "4" if MIPS_L1_CACHE_SHIFT_4
383 Select this if your system includes an L2 cache and you want U-Boot
384 to initialise & maintain it.
386 config DYNAMIC_IO_PORT_BASE
392 Select this if your system contains a MIPS Coherence Manager and you
393 wish U-Boot to configure it or make use of it to retrieve system
394 information such as cache configuration.
400 The physical base address at which to map the MIPS Coherence Manager
401 Global Configuration Registers (GCRs). This should be set such that
402 the GCRs occupy a region of the physical address space which is
403 otherwise unused, or at minimum that software doesn't need to access.