1 menu "MIPS architecture"
8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
12 prompt "Target select"
15 config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
17 select SUPPORTS_BIG_ENDIAN
18 select SUPPORTS_LITTLE_ENDIAN
19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
28 select DYNAMIC_IO_PORT_BASE
33 select SUPPORTS_BIG_ENDIAN
34 select SUPPORTS_LITTLE_ENDIAN
35 select SUPPORTS_CPU_MIPS32_R1
36 select SUPPORTS_CPU_MIPS32_R2
37 select SUPPORTS_CPU_MIPS32_R6
38 select SUPPORTS_CPU_MIPS64_R1
39 select SUPPORTS_CPU_MIPS64_R2
40 select SUPPORTS_CPU_MIPS64_R6
42 select MIPS_L1_CACHE_SHIFT_6
46 select SUPPORTS_BIG_ENDIAN
47 select SUPPORTS_CPU_MIPS32_R1
48 select SUPPORTS_CPU_MIPS32_R2
49 select SYS_MIPS_CACHE_INIT_RAM_LOAD
51 config TARGET_DBAU1X00
52 bool "Support dbau1x00"
53 select SUPPORTS_BIG_ENDIAN
54 select SUPPORTS_LITTLE_ENDIAN
55 select SUPPORTS_CPU_MIPS32_R1
56 select SUPPORTS_CPU_MIPS32_R2
57 select SYS_MIPS_CACHE_INIT_RAM_LOAD
62 select SUPPORTS_LITTLE_ENDIAN
63 select SUPPORTS_CPU_MIPS32_R1
64 select SUPPORTS_CPU_MIPS32_R2
65 select SYS_MIPS_CACHE_INIT_RAM_LOAD
69 bool "Support QCA/Atheros ath79"
74 bool "Support Microchip PIC32"
79 bool "Support Imagination Xilfpga"
85 select SUPPORTS_LITTLE_ENDIAN
86 select SUPPORTS_CPU_MIPS32_R1
87 select SUPPORTS_CPU_MIPS32_R2
88 select MIPS_L1_CACHE_SHIFT_4
90 This supports IMGTEC MIPSfpga platform
94 source "board/dbau1x00/Kconfig"
95 source "board/imgtec/malta/Kconfig"
96 source "board/imgtec/xilfpga/Kconfig"
97 source "board/micronas/vct/Kconfig"
98 source "board/pb1x00/Kconfig"
99 source "board/qemu-mips/Kconfig"
100 source "arch/mips/mach-ath79/Kconfig"
101 source "arch/mips/mach-pic32/Kconfig"
106 prompt "Endianness selection"
108 Some MIPS boards can be configured for either little or big endian
109 byte order. These modes require different U-Boot images. In general there
110 is one preferred byteorder for a particular system but some systems are
111 just as commonly used in the one or the other endianness.
113 config SYS_BIG_ENDIAN
115 depends on SUPPORTS_BIG_ENDIAN
117 config SYS_LITTLE_ENDIAN
119 depends on SUPPORTS_LITTLE_ENDIAN
124 prompt "CPU selection"
125 default CPU_MIPS32_R2
128 bool "MIPS32 Release 1"
129 depends on SUPPORTS_CPU_MIPS32_R1
132 Choose this option to build an U-Boot for release 1 through 5 of the
136 bool "MIPS32 Release 2"
137 depends on SUPPORTS_CPU_MIPS32_R2
140 Choose this option to build an U-Boot for release 2 through 5 of the
144 bool "MIPS32 Release 6"
145 depends on SUPPORTS_CPU_MIPS32_R6
148 Choose this option to build an U-Boot for release 6 or later of the
152 bool "MIPS64 Release 1"
153 depends on SUPPORTS_CPU_MIPS64_R1
156 Choose this option to build a kernel for release 1 through 5 of the
160 bool "MIPS64 Release 2"
161 depends on SUPPORTS_CPU_MIPS64_R2
164 Choose this option to build a kernel for release 2 through 5 of the
168 bool "MIPS64 Release 6"
169 depends on SUPPORTS_CPU_MIPS64_R6
172 Choose this option to build a kernel for release 6 or later of the
177 menu "OS boot interface"
179 config MIPS_BOOT_CMDLINE_LEGACY
180 bool "Hand over legacy command line to Linux kernel"
183 Enable this option if you want U-Boot to hand over the Yamon-style
184 command line to the kernel. All bootargs will be prepared as argc/argv
185 compatible list. The argument count (argc) is stored in register $a0.
186 The address of the argument list (argv) is stored in register $a1.
188 config MIPS_BOOT_ENV_LEGACY
189 bool "Hand over legacy environment to Linux kernel"
192 Enable this option if you want U-Boot to hand over the Yamon-style
193 environment to the kernel. Information like memory size, initrd
194 address and size will be prepared as zero-terminated key/value list.
195 The address of the environment is stored in register $a2.
198 bool "Hand over a flattened device tree to Linux kernel"
201 Enable this option if you want U-Boot to hand over a flattened
202 device tree to the kernel. According to UHI register $a0 will be set
203 to -2 and the FDT address is stored in $a1.
207 config SUPPORTS_BIG_ENDIAN
210 config SUPPORTS_LITTLE_ENDIAN
213 config SUPPORTS_CPU_MIPS32_R1
216 config SUPPORTS_CPU_MIPS32_R2
219 config SUPPORTS_CPU_MIPS32_R6
222 config SUPPORTS_CPU_MIPS64_R1
225 config SUPPORTS_CPU_MIPS64_R2
228 config SUPPORTS_CPU_MIPS64_R6
233 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
237 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
242 config MIPS_TUNE_14KC
245 config MIPS_TUNE_24KC
248 config MIPS_TUNE_34KC
251 config MIPS_TUNE_74KC
263 config SYS_MIPS_CACHE_INIT_RAM_LOAD
266 config SYS_DCACHE_SIZE
270 The total size of the L1 Dcache, if known at compile time.
272 config SYS_DCACHE_LINE_SIZE
276 The size of L1 Dcache lines, if known at compile time.
278 config SYS_ICACHE_SIZE
282 The total size of the L1 ICache, if known at compile time.
284 config SYS_ICACHE_LINE_SIZE
288 The size of L1 Icache lines, if known at compile time.
290 config SYS_CACHE_SIZE_AUTO
291 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
292 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
294 Select this (or let it be auto-selected by not defining any cache
295 sizes) in order to allow U-Boot to automatically detect the sizes
296 of caches at runtime. This has a small cost in code size & runtime
297 so if you know the cache configuration for your system at compile
298 time it would be beneficial to configure it.
300 config MIPS_L1_CACHE_SHIFT_4
303 config MIPS_L1_CACHE_SHIFT_5
306 config MIPS_L1_CACHE_SHIFT_6
309 config MIPS_L1_CACHE_SHIFT_7
312 config MIPS_L1_CACHE_SHIFT
314 default "7" if MIPS_L1_CACHE_SHIFT_7
315 default "6" if MIPS_L1_CACHE_SHIFT_6
316 default "5" if MIPS_L1_CACHE_SHIFT_5
317 default "4" if MIPS_L1_CACHE_SHIFT_4
323 Select this if your system includes an L2 cache and you want U-Boot
324 to initialise & maintain it.
326 config DYNAMIC_IO_PORT_BASE
332 Select this if your system contains a MIPS Coherence Manager and you
333 wish U-Boot to configure it or make use of it to retrieve system
334 information such as cache configuration.
340 The physical base address at which to map the MIPS Coherence Manager
341 Global Configuration Registers (GCRs). This should be set such that
342 the GCRs occupy a region of the physical address space which is
343 otherwise unused, or at minimum that software doesn't need to access.