1 menu "MIPS architecture"
8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
12 prompt "Target select"
15 config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
17 select SUPPORTS_BIG_ENDIAN
18 select SUPPORTS_LITTLE_ENDIAN
19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
28 select DYNAMIC_IO_PORT_BASE
31 select SUPPORTS_BIG_ENDIAN
32 select SUPPORTS_LITTLE_ENDIAN
33 select SUPPORTS_CPU_MIPS32_R1
34 select SUPPORTS_CPU_MIPS32_R2
35 select SUPPORTS_CPU_MIPS32_R6
36 select SUPPORTS_CPU_MIPS64_R1
37 select SUPPORTS_CPU_MIPS64_R2
38 select SUPPORTS_CPU_MIPS64_R6
40 select MIPS_L1_CACHE_SHIFT_6
44 select SUPPORTS_BIG_ENDIAN
45 select SUPPORTS_CPU_MIPS32_R1
46 select SUPPORTS_CPU_MIPS32_R2
47 select SYS_MIPS_CACHE_INIT_RAM_LOAD
49 config TARGET_DBAU1X00
50 bool "Support dbau1x00"
51 select SUPPORTS_BIG_ENDIAN
52 select SUPPORTS_LITTLE_ENDIAN
53 select SUPPORTS_CPU_MIPS32_R1
54 select SUPPORTS_CPU_MIPS32_R2
55 select SYS_MIPS_CACHE_INIT_RAM_LOAD
60 select SUPPORTS_LITTLE_ENDIAN
61 select SUPPORTS_CPU_MIPS32_R1
62 select SUPPORTS_CPU_MIPS32_R2
63 select SYS_MIPS_CACHE_INIT_RAM_LOAD
67 bool "Support QCA/Atheros ath79"
72 bool "Support Microchip PIC32"
77 bool "Support Imagination Xilfpga"
83 select SUPPORTS_LITTLE_ENDIAN
84 select SUPPORTS_CPU_MIPS32_R1
85 select SUPPORTS_CPU_MIPS32_R2
86 select MIPS_L1_CACHE_SHIFT_4
88 This supports IMGTEC MIPSfpga platform
92 source "board/dbau1x00/Kconfig"
93 source "board/imgtec/malta/Kconfig"
94 source "board/imgtec/xilfpga/Kconfig"
95 source "board/micronas/vct/Kconfig"
96 source "board/pb1x00/Kconfig"
97 source "board/qemu-mips/Kconfig"
98 source "arch/mips/mach-ath79/Kconfig"
99 source "arch/mips/mach-pic32/Kconfig"
104 prompt "Endianness selection"
106 Some MIPS boards can be configured for either little or big endian
107 byte order. These modes require different U-Boot images. In general there
108 is one preferred byteorder for a particular system but some systems are
109 just as commonly used in the one or the other endianness.
111 config SYS_BIG_ENDIAN
113 depends on SUPPORTS_BIG_ENDIAN
115 config SYS_LITTLE_ENDIAN
117 depends on SUPPORTS_LITTLE_ENDIAN
122 prompt "CPU selection"
123 default CPU_MIPS32_R2
126 bool "MIPS32 Release 1"
127 depends on SUPPORTS_CPU_MIPS32_R1
130 Choose this option to build an U-Boot for release 1 through 5 of the
134 bool "MIPS32 Release 2"
135 depends on SUPPORTS_CPU_MIPS32_R2
138 Choose this option to build an U-Boot for release 2 through 5 of the
142 bool "MIPS32 Release 6"
143 depends on SUPPORTS_CPU_MIPS32_R6
146 Choose this option to build an U-Boot for release 6 or later of the
150 bool "MIPS64 Release 1"
151 depends on SUPPORTS_CPU_MIPS64_R1
154 Choose this option to build a kernel for release 1 through 5 of the
158 bool "MIPS64 Release 2"
159 depends on SUPPORTS_CPU_MIPS64_R2
162 Choose this option to build a kernel for release 2 through 5 of the
166 bool "MIPS64 Release 6"
167 depends on SUPPORTS_CPU_MIPS64_R6
170 Choose this option to build a kernel for release 6 or later of the
175 menu "OS boot interface"
177 config MIPS_BOOT_CMDLINE_LEGACY
178 bool "Hand over legacy command line to Linux kernel"
181 Enable this option if you want U-Boot to hand over the Yamon-style
182 command line to the kernel. All bootargs will be prepared as argc/argv
183 compatible list. The argument count (argc) is stored in register $a0.
184 The address of the argument list (argv) is stored in register $a1.
186 config MIPS_BOOT_ENV_LEGACY
187 bool "Hand over legacy environment to Linux kernel"
190 Enable this option if you want U-Boot to hand over the Yamon-style
191 environment to the kernel. Information like memory size, initrd
192 address and size will be prepared as zero-terminated key/value list.
193 The address of the environment is stored in register $a2.
196 bool "Hand over a flattened device tree to Linux kernel"
199 Enable this option if you want U-Boot to hand over a flattened
200 device tree to the kernel. According to UHI register $a0 will be set
201 to -2 and the FDT address is stored in $a1.
205 config SUPPORTS_BIG_ENDIAN
208 config SUPPORTS_LITTLE_ENDIAN
211 config SUPPORTS_CPU_MIPS32_R1
214 config SUPPORTS_CPU_MIPS32_R2
217 config SUPPORTS_CPU_MIPS32_R6
220 config SUPPORTS_CPU_MIPS64_R1
223 config SUPPORTS_CPU_MIPS64_R2
226 config SUPPORTS_CPU_MIPS64_R6
231 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
235 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
240 config MIPS_TUNE_14KC
243 config MIPS_TUNE_24KC
246 config MIPS_TUNE_34KC
249 config MIPS_TUNE_74KC
261 config SYS_MIPS_CACHE_INIT_RAM_LOAD
264 config SYS_DCACHE_SIZE
268 The total size of the L1 Dcache, if known at compile time.
270 config SYS_DCACHE_LINE_SIZE
274 The size of L1 Dcache lines, if known at compile time.
276 config SYS_ICACHE_SIZE
280 The total size of the L1 ICache, if known at compile time.
282 config SYS_ICACHE_LINE_SIZE
286 The size of L1 Icache lines, if known at compile time.
288 config SYS_CACHE_SIZE_AUTO
289 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
290 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
292 Select this (or let it be auto-selected by not defining any cache
293 sizes) in order to allow U-Boot to automatically detect the sizes
294 of caches at runtime. This has a small cost in code size & runtime
295 so if you know the cache configuration for your system at compile
296 time it would be beneficial to configure it.
298 config MIPS_L1_CACHE_SHIFT_4
301 config MIPS_L1_CACHE_SHIFT_5
304 config MIPS_L1_CACHE_SHIFT_6
307 config MIPS_L1_CACHE_SHIFT_7
310 config MIPS_L1_CACHE_SHIFT
312 default "7" if MIPS_L1_CACHE_SHIFT_7
313 default "6" if MIPS_L1_CACHE_SHIFT_6
314 default "5" if MIPS_L1_CACHE_SHIFT_5
315 default "4" if MIPS_L1_CACHE_SHIFT_4
321 Select this if your system includes an L2 cache and you want U-Boot
322 to initialise & maintain it.
324 config DYNAMIC_IO_PORT_BASE
330 Select this if your system contains a MIPS Coherence Manager and you
331 wish U-Boot to configure it or make use of it to retrieve system
332 information such as cache configuration.
338 The physical base address at which to map the MIPS Coherence Manager
339 Global Configuration Registers (GCRs). This should be set such that
340 the GCRs occupy a region of the physical address space which is
341 otherwise unused, or at minimum that software doesn't need to access.