1 menu "MIPS architecture"
8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
12 prompt "Target select"
15 config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
17 select SUPPORTS_BIG_ENDIAN
18 select SUPPORTS_LITTLE_ENDIAN
19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
23 select ROM_EXCEPTION_VECTORS
30 select DYNAMIC_IO_PORT_BASE
35 select SUPPORTS_BIG_ENDIAN
36 select SUPPORTS_LITTLE_ENDIAN
37 select SUPPORTS_CPU_MIPS32_R1
38 select SUPPORTS_CPU_MIPS32_R2
39 select SUPPORTS_CPU_MIPS32_R6
40 select SUPPORTS_CPU_MIPS64_R1
41 select SUPPORTS_CPU_MIPS64_R2
42 select SUPPORTS_CPU_MIPS64_R6
44 select MIPS_L1_CACHE_SHIFT_6
45 select ROM_EXCEPTION_VECTORS
50 select SUPPORTS_BIG_ENDIAN
51 select SUPPORTS_CPU_MIPS32_R1
52 select SUPPORTS_CPU_MIPS32_R2
53 select SYS_MIPS_CACHE_INIT_RAM_LOAD
54 select ROM_EXCEPTION_VECTORS
56 config TARGET_DBAU1X00
57 bool "Support dbau1x00"
58 select SUPPORTS_BIG_ENDIAN
59 select SUPPORTS_LITTLE_ENDIAN
60 select SUPPORTS_CPU_MIPS32_R1
61 select SUPPORTS_CPU_MIPS32_R2
62 select SYS_MIPS_CACHE_INIT_RAM_LOAD
63 select ROM_EXCEPTION_VECTORS
68 select SUPPORTS_LITTLE_ENDIAN
69 select SUPPORTS_CPU_MIPS32_R1
70 select SUPPORTS_CPU_MIPS32_R2
71 select SYS_MIPS_CACHE_INIT_RAM_LOAD
72 select ROM_EXCEPTION_VECTORS
76 bool "Support QCA/Atheros ath79"
81 bool "Support BMIPS SoCs"
91 bool "Support Microchip PIC32"
101 select MIPS_L1_CACHE_SHIFT_6
103 select OF_BOARD_SETUP
104 select SUPPORTS_BIG_ENDIAN
105 select SUPPORTS_LITTLE_ENDIAN
106 select SUPPORTS_CPU_MIPS32_R1
107 select SUPPORTS_CPU_MIPS32_R2
108 select SUPPORTS_CPU_MIPS32_R6
109 select SUPPORTS_CPU_MIPS64_R1
110 select SUPPORTS_CPU_MIPS64_R2
111 select SUPPORTS_CPU_MIPS64_R6
112 select ROM_EXCEPTION_VECTORS
113 imply ENV_IS_IN_FLASH
115 config TARGET_XILFPGA
116 bool "Support Imagination Xilfpga"
122 select SUPPORTS_LITTLE_ENDIAN
123 select SUPPORTS_CPU_MIPS32_R1
124 select SUPPORTS_CPU_MIPS32_R2
125 select MIPS_L1_CACHE_SHIFT_4
126 select ROM_EXCEPTION_VECTORS
128 This supports IMGTEC MIPSfpga platform
132 source "board/dbau1x00/Kconfig"
133 source "board/imgtec/boston/Kconfig"
134 source "board/imgtec/malta/Kconfig"
135 source "board/imgtec/xilfpga/Kconfig"
136 source "board/micronas/vct/Kconfig"
137 source "board/pb1x00/Kconfig"
138 source "board/qemu-mips/Kconfig"
139 source "arch/mips/mach-ath79/Kconfig"
140 source "arch/mips/mach-bmips/Kconfig"
141 source "arch/mips/mach-pic32/Kconfig"
146 prompt "Endianness selection"
148 Some MIPS boards can be configured for either little or big endian
149 byte order. These modes require different U-Boot images. In general there
150 is one preferred byteorder for a particular system but some systems are
151 just as commonly used in the one or the other endianness.
153 config SYS_BIG_ENDIAN
155 depends on SUPPORTS_BIG_ENDIAN
157 config SYS_LITTLE_ENDIAN
159 depends on SUPPORTS_LITTLE_ENDIAN
164 prompt "CPU selection"
165 default CPU_MIPS32_R2
168 bool "MIPS32 Release 1"
169 depends on SUPPORTS_CPU_MIPS32_R1
172 Choose this option to build an U-Boot for release 1 through 5 of the
176 bool "MIPS32 Release 2"
177 depends on SUPPORTS_CPU_MIPS32_R2
180 Choose this option to build an U-Boot for release 2 through 5 of the
184 bool "MIPS32 Release 6"
185 depends on SUPPORTS_CPU_MIPS32_R6
188 Choose this option to build an U-Boot for release 6 or later of the
192 bool "MIPS64 Release 1"
193 depends on SUPPORTS_CPU_MIPS64_R1
196 Choose this option to build a kernel for release 1 through 5 of the
200 bool "MIPS64 Release 2"
201 depends on SUPPORTS_CPU_MIPS64_R2
203 imply ENV_IS_IN_FLASH
205 Choose this option to build a kernel for release 2 through 5 of the
209 bool "MIPS64 Release 6"
210 depends on SUPPORTS_CPU_MIPS64_R6
213 Choose this option to build a kernel for release 6 or later of the
220 config ROM_EXCEPTION_VECTORS
221 bool "Build U-Boot image with exception vectors"
223 Enable this to include exception vectors in the U-Boot image. This is
224 required if the U-Boot entry point is equal to the address of the
225 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
226 U-Boot booted from parallel NOR flash).
227 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
228 In that case the image size will be reduced by 0x500 bytes.
231 hex "MIPS CM GCR Base Address"
233 default 0x16100000 if TARGET_BOSTON
236 The physical base address at which to map the MIPS Coherence Manager
237 Global Configuration Registers (GCRs). This should be set such that
238 the GCRs occupy a region of the physical address space which is
239 otherwise unused, or at minimum that software doesn't need to access.
243 menu "OS boot interface"
245 config MIPS_BOOT_CMDLINE_LEGACY
246 bool "Hand over legacy command line to Linux kernel"
249 Enable this option if you want U-Boot to hand over the Yamon-style
250 command line to the kernel. All bootargs will be prepared as argc/argv
251 compatible list. The argument count (argc) is stored in register $a0.
252 The address of the argument list (argv) is stored in register $a1.
254 config MIPS_BOOT_ENV_LEGACY
255 bool "Hand over legacy environment to Linux kernel"
258 Enable this option if you want U-Boot to hand over the Yamon-style
259 environment to the kernel. Information like memory size, initrd
260 address and size will be prepared as zero-terminated key/value list.
261 The address of the environment is stored in register $a2.
264 bool "Hand over a flattened device tree to Linux kernel"
267 Enable this option if you want U-Boot to hand over a flattened
268 device tree to the kernel. According to UHI register $a0 will be set
269 to -2 and the FDT address is stored in $a1.
273 config SUPPORTS_BIG_ENDIAN
276 config SUPPORTS_LITTLE_ENDIAN
279 config SUPPORTS_CPU_MIPS32_R1
282 config SUPPORTS_CPU_MIPS32_R2
285 config SUPPORTS_CPU_MIPS32_R6
288 config SUPPORTS_CPU_MIPS64_R1
291 config SUPPORTS_CPU_MIPS64_R2
294 config SUPPORTS_CPU_MIPS64_R6
299 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
303 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
308 config MIPS_TUNE_14KC
311 config MIPS_TUNE_24KC
314 config MIPS_TUNE_34KC
317 config MIPS_TUNE_74KC
329 config SYS_MIPS_CACHE_INIT_RAM_LOAD
332 config MIPS_INIT_STACK_IN_SRAM
336 Select this if the initial stack frame could be setup in SRAM.
337 Normally the initial stack frame is set up in DRAM which is often
338 only available after lowlevel_init. With this option the initial
339 stack frame and the early C environment is set up before
340 lowlevel_init. Thus lowlevel_init does not need to be implemented
343 config SYS_DCACHE_SIZE
347 The total size of the L1 Dcache, if known at compile time.
349 config SYS_DCACHE_LINE_SIZE
353 The size of L1 Dcache lines, if known at compile time.
355 config SYS_ICACHE_SIZE
359 The total size of the L1 ICache, if known at compile time.
361 config SYS_ICACHE_LINE_SIZE
365 The size of L1 Icache lines, if known at compile time.
367 config SYS_CACHE_SIZE_AUTO
368 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
369 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
371 Select this (or let it be auto-selected by not defining any cache
372 sizes) in order to allow U-Boot to automatically detect the sizes
373 of caches at runtime. This has a small cost in code size & runtime
374 so if you know the cache configuration for your system at compile
375 time it would be beneficial to configure it.
377 config MIPS_L1_CACHE_SHIFT_4
380 config MIPS_L1_CACHE_SHIFT_5
383 config MIPS_L1_CACHE_SHIFT_6
386 config MIPS_L1_CACHE_SHIFT_7
389 config MIPS_L1_CACHE_SHIFT
391 default "7" if MIPS_L1_CACHE_SHIFT_7
392 default "6" if MIPS_L1_CACHE_SHIFT_6
393 default "5" if MIPS_L1_CACHE_SHIFT_5
394 default "4" if MIPS_L1_CACHE_SHIFT_4
400 Select this if your system includes an L2 cache and you want U-Boot
401 to initialise & maintain it.
403 config DYNAMIC_IO_PORT_BASE
409 Select this if your system contains a MIPS Coherence Manager and you
410 wish U-Boot to configure it or make use of it to retrieve system
411 information such as cache configuration.