1 menu "MIPS architecture"
8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
12 prompt "Target select"
15 config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
17 select SUPPORTS_BIG_ENDIAN
18 select SUPPORTS_LITTLE_ENDIAN
19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
28 select DYNAMIC_IO_PORT_BASE
31 select SUPPORTS_BIG_ENDIAN
32 select SUPPORTS_LITTLE_ENDIAN
33 select SUPPORTS_CPU_MIPS32_R1
34 select SUPPORTS_CPU_MIPS32_R2
35 select SUPPORTS_CPU_MIPS32_R6
36 select SUPPORTS_CPU_MIPS64_R1
37 select SUPPORTS_CPU_MIPS64_R2
38 select SUPPORTS_CPU_MIPS64_R6
40 select MIPS_L1_CACHE_SHIFT_6
44 select SUPPORTS_BIG_ENDIAN
45 select SUPPORTS_CPU_MIPS32_R1
46 select SUPPORTS_CPU_MIPS32_R2
47 select SYS_MIPS_CACHE_INIT_RAM_LOAD
49 config TARGET_DBAU1X00
50 bool "Support dbau1x00"
51 select SUPPORTS_BIG_ENDIAN
52 select SUPPORTS_LITTLE_ENDIAN
53 select SUPPORTS_CPU_MIPS32_R1
54 select SUPPORTS_CPU_MIPS32_R2
55 select SYS_MIPS_CACHE_INIT_RAM_LOAD
60 select SUPPORTS_LITTLE_ENDIAN
61 select SUPPORTS_CPU_MIPS32_R1
62 select SUPPORTS_CPU_MIPS32_R2
63 select SYS_MIPS_CACHE_INIT_RAM_LOAD
67 bool "Support QCA/Atheros ath79"
72 bool "Support Microchip PIC32"
78 source "board/dbau1x00/Kconfig"
79 source "board/imgtec/malta/Kconfig"
80 source "board/micronas/vct/Kconfig"
81 source "board/pb1x00/Kconfig"
82 source "board/qemu-mips/Kconfig"
83 source "arch/mips/mach-ath79/Kconfig"
84 source "arch/mips/mach-pic32/Kconfig"
89 prompt "Endianness selection"
91 Some MIPS boards can be configured for either little or big endian
92 byte order. These modes require different U-Boot images. In general there
93 is one preferred byteorder for a particular system but some systems are
94 just as commonly used in the one or the other endianness.
98 depends on SUPPORTS_BIG_ENDIAN
100 config SYS_LITTLE_ENDIAN
102 depends on SUPPORTS_LITTLE_ENDIAN
107 prompt "CPU selection"
108 default CPU_MIPS32_R2
111 bool "MIPS32 Release 1"
112 depends on SUPPORTS_CPU_MIPS32_R1
115 Choose this option to build an U-Boot for release 1 through 5 of the
119 bool "MIPS32 Release 2"
120 depends on SUPPORTS_CPU_MIPS32_R2
123 Choose this option to build an U-Boot for release 2 through 5 of the
127 bool "MIPS32 Release 6"
128 depends on SUPPORTS_CPU_MIPS32_R6
131 Choose this option to build an U-Boot for release 6 or later of the
135 bool "MIPS64 Release 1"
136 depends on SUPPORTS_CPU_MIPS64_R1
139 Choose this option to build a kernel for release 1 through 5 of the
143 bool "MIPS64 Release 2"
144 depends on SUPPORTS_CPU_MIPS64_R2
147 Choose this option to build a kernel for release 2 through 5 of the
151 bool "MIPS64 Release 6"
152 depends on SUPPORTS_CPU_MIPS64_R6
155 Choose this option to build a kernel for release 6 or later of the
160 menu "OS boot interface"
162 config MIPS_BOOT_CMDLINE_LEGACY
163 bool "Hand over legacy command line to Linux kernel"
166 Enable this option if you want U-Boot to hand over the Yamon-style
167 command line to the kernel. All bootargs will be prepared as argc/argv
168 compatible list. The argument count (argc) is stored in register $a0.
169 The address of the argument list (argv) is stored in register $a1.
171 config MIPS_BOOT_ENV_LEGACY
172 bool "Hand over legacy environment to Linux kernel"
175 Enable this option if you want U-Boot to hand over the Yamon-style
176 environment to the kernel. Information like memory size, initrd
177 address and size will be prepared as zero-terminated key/value list.
178 The address of the environment is stored in register $a2.
181 bool "Hand over a flattened device tree to Linux kernel"
184 Enable this option if you want U-Boot to hand over a flattened
185 device tree to the kernel. According to UHI register $a0 will be set
186 to -2 and the FDT address is stored in $a1.
190 config SUPPORTS_BIG_ENDIAN
193 config SUPPORTS_LITTLE_ENDIAN
196 config SUPPORTS_CPU_MIPS32_R1
199 config SUPPORTS_CPU_MIPS32_R2
202 config SUPPORTS_CPU_MIPS32_R6
205 config SUPPORTS_CPU_MIPS64_R1
208 config SUPPORTS_CPU_MIPS64_R2
211 config SUPPORTS_CPU_MIPS64_R6
216 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
220 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
225 config MIPS_TUNE_14KC
228 config MIPS_TUNE_24KC
231 config MIPS_TUNE_74KC
243 config SYS_MIPS_CACHE_INIT_RAM_LOAD
246 config MIPS_L1_CACHE_SHIFT_4
249 config MIPS_L1_CACHE_SHIFT_5
252 config MIPS_L1_CACHE_SHIFT_6
255 config MIPS_L1_CACHE_SHIFT_7
258 config MIPS_L1_CACHE_SHIFT
260 default "7" if MIPS_L1_CACHE_SHIFT_7
261 default "6" if MIPS_L1_CACHE_SHIFT_6
262 default "5" if MIPS_L1_CACHE_SHIFT_5
263 default "4" if MIPS_L1_CACHE_SHIFT_4
266 config DYNAMIC_IO_PORT_BASE