1 menu "MIPS architecture"
8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
12 prompt "Target select"
15 config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
17 select ROM_EXCEPTION_VECTORS
18 select SUPPORTS_BIG_ENDIAN
19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
23 select SUPPORTS_LITTLE_ENDIAN
29 select DYNAMIC_IO_PORT_BASE
31 select MIPS_INSERT_BOOT_CONFIG
32 select MIPS_L1_CACHE_SHIFT_6
36 select ROM_EXCEPTION_VECTORS
37 select SUPPORTS_BIG_ENDIAN
38 select SUPPORTS_CPU_MIPS32_R1
39 select SUPPORTS_CPU_MIPS32_R2
40 select SUPPORTS_CPU_MIPS32_R6
41 select SUPPORTS_CPU_MIPS64_R1
42 select SUPPORTS_CPU_MIPS64_R2
43 select SUPPORTS_CPU_MIPS64_R6
44 select SUPPORTS_LITTLE_ENDIAN
50 select ROM_EXCEPTION_VECTORS
51 select SUPPORTS_BIG_ENDIAN
52 select SUPPORTS_CPU_MIPS32_R1
53 select SUPPORTS_CPU_MIPS32_R2
54 select SYS_MIPS_CACHE_INIT_RAM_LOAD
57 bool "Support QCA/Atheros ath79"
63 bool "Support BMIPS SoCs"
73 bool "Support MT7620/7688 SoCs"
75 select DISPLAY_CPUINFO
82 select ROM_EXCEPTION_VECTORS
83 select SUPPORTS_CPU_MIPS32_R1
84 select SUPPORTS_CPU_MIPS32_R2
85 select SUPPORTS_LITTLE_ENDIAN
88 bool "Support Microchip PIC32"
98 select MIPS_L1_CACHE_SHIFT_6
100 select OF_BOARD_SETUP
102 select ROM_EXCEPTION_VECTORS
103 select SUPPORTS_BIG_ENDIAN
104 select SUPPORTS_CPU_MIPS32_R1
105 select SUPPORTS_CPU_MIPS32_R2
106 select SUPPORTS_CPU_MIPS32_R6
107 select SUPPORTS_CPU_MIPS64_R1
108 select SUPPORTS_CPU_MIPS64_R2
109 select SUPPORTS_CPU_MIPS64_R6
110 select SUPPORTS_LITTLE_ENDIAN
113 config TARGET_XILFPGA
114 bool "Support Imagination Xilfpga"
119 select MIPS_L1_CACHE_SHIFT_4
121 select ROM_EXCEPTION_VECTORS
122 select SUPPORTS_CPU_MIPS32_R1
123 select SUPPORTS_CPU_MIPS32_R2
124 select SUPPORTS_LITTLE_ENDIAN
127 This supports IMGTEC MIPSfpga platform
131 source "board/imgtec/boston/Kconfig"
132 source "board/imgtec/malta/Kconfig"
133 source "board/imgtec/xilfpga/Kconfig"
134 source "board/micronas/vct/Kconfig"
135 source "board/qemu-mips/Kconfig"
136 source "arch/mips/mach-ath79/Kconfig"
137 source "arch/mips/mach-bmips/Kconfig"
138 source "arch/mips/mach-pic32/Kconfig"
139 source "arch/mips/mach-mt7620/Kconfig"
144 prompt "Endianness selection"
146 Some MIPS boards can be configured for either little or big endian
147 byte order. These modes require different U-Boot images. In general there
148 is one preferred byteorder for a particular system but some systems are
149 just as commonly used in the one or the other endianness.
151 config SYS_BIG_ENDIAN
153 depends on SUPPORTS_BIG_ENDIAN
155 config SYS_LITTLE_ENDIAN
157 depends on SUPPORTS_LITTLE_ENDIAN
162 prompt "CPU selection"
163 default CPU_MIPS32_R2
166 bool "MIPS32 Release 1"
167 depends on SUPPORTS_CPU_MIPS32_R1
170 Choose this option to build an U-Boot for release 1 through 5 of the
174 bool "MIPS32 Release 2"
175 depends on SUPPORTS_CPU_MIPS32_R2
178 Choose this option to build an U-Boot for release 2 through 5 of the
182 bool "MIPS32 Release 6"
183 depends on SUPPORTS_CPU_MIPS32_R6
186 Choose this option to build an U-Boot for release 6 or later of the
190 bool "MIPS64 Release 1"
191 depends on SUPPORTS_CPU_MIPS64_R1
194 Choose this option to build a kernel for release 1 through 5 of the
198 bool "MIPS64 Release 2"
199 depends on SUPPORTS_CPU_MIPS64_R2
202 Choose this option to build a kernel for release 2 through 5 of the
206 bool "MIPS64 Release 6"
207 depends on SUPPORTS_CPU_MIPS64_R6
210 Choose this option to build a kernel for release 6 or later of the
217 config ROM_EXCEPTION_VECTORS
218 bool "Build U-Boot image with exception vectors"
220 Enable this to include exception vectors in the U-Boot image. This is
221 required if the U-Boot entry point is equal to the address of the
222 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
223 U-Boot booted from parallel NOR flash).
224 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
225 In that case the image size will be reduced by 0x500 bytes.
228 hex "MIPS CM GCR Base Address"
230 default 0x16100000 if TARGET_BOSTON
233 The physical base address at which to map the MIPS Coherence Manager
234 Global Configuration Registers (GCRs). This should be set such that
235 the GCRs occupy a region of the physical address space which is
236 otherwise unused, or at minimum that software doesn't need to access.
238 config MIPS_CACHE_INDEX_BASE
239 hex "Index base address for cache initialisation"
240 default 0x80000000 if CPU_MIPS32
241 default 0xffffffff80000000 if CPU_MIPS64
243 This is the base address for a memory block, which is used for
244 initialising the cache lines. This is also the base address of a memory
245 block which is used for loading and filling cache lines when
246 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
247 Normally this is CKSEG0. If the MIPS system needs to move this block
248 to some SRAM or ScratchPad RAM, adapt this option accordingly.
252 menu "OS boot interface"
254 config MIPS_BOOT_CMDLINE_LEGACY
255 bool "Hand over legacy command line to Linux kernel"
258 Enable this option if you want U-Boot to hand over the Yamon-style
259 command line to the kernel. All bootargs will be prepared as argc/argv
260 compatible list. The argument count (argc) is stored in register $a0.
261 The address of the argument list (argv) is stored in register $a1.
263 config MIPS_BOOT_ENV_LEGACY
264 bool "Hand over legacy environment to Linux kernel"
267 Enable this option if you want U-Boot to hand over the Yamon-style
268 environment to the kernel. Information like memory size, initrd
269 address and size will be prepared as zero-terminated key/value list.
270 The address of the environment is stored in register $a2.
273 bool "Hand over a flattened device tree to Linux kernel"
276 Enable this option if you want U-Boot to hand over a flattened
277 device tree to the kernel. According to UHI register $a0 will be set
278 to -2 and the FDT address is stored in $a1.
282 config SUPPORTS_BIG_ENDIAN
285 config SUPPORTS_LITTLE_ENDIAN
288 config SUPPORTS_CPU_MIPS32_R1
291 config SUPPORTS_CPU_MIPS32_R2
294 config SUPPORTS_CPU_MIPS32_R6
297 config SUPPORTS_CPU_MIPS64_R1
300 config SUPPORTS_CPU_MIPS64_R2
303 config SUPPORTS_CPU_MIPS64_R6
308 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
312 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
317 config MIPS_TUNE_14KC
320 config MIPS_TUNE_24KC
323 config MIPS_TUNE_34KC
326 config MIPS_TUNE_74KC
338 config SYS_MIPS_CACHE_INIT_RAM_LOAD
341 config MIPS_INIT_STACK_IN_SRAM
345 Select this if the initial stack frame could be setup in SRAM.
346 Normally the initial stack frame is set up in DRAM which is often
347 only available after lowlevel_init. With this option the initial
348 stack frame and the early C environment is set up before
349 lowlevel_init. Thus lowlevel_init does not need to be implemented
352 config SYS_DCACHE_SIZE
356 The total size of the L1 Dcache, if known at compile time.
358 config SYS_DCACHE_LINE_SIZE
362 The size of L1 Dcache lines, if known at compile time.
364 config SYS_ICACHE_SIZE
368 The total size of the L1 ICache, if known at compile time.
370 config SYS_ICACHE_LINE_SIZE
374 The size of L1 Icache lines, if known at compile time.
376 config SYS_CACHE_SIZE_AUTO
377 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
378 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
380 Select this (or let it be auto-selected by not defining any cache
381 sizes) in order to allow U-Boot to automatically detect the sizes
382 of caches at runtime. This has a small cost in code size & runtime
383 so if you know the cache configuration for your system at compile
384 time it would be beneficial to configure it.
386 config MIPS_L1_CACHE_SHIFT_4
389 config MIPS_L1_CACHE_SHIFT_5
392 config MIPS_L1_CACHE_SHIFT_6
395 config MIPS_L1_CACHE_SHIFT_7
398 config MIPS_L1_CACHE_SHIFT
400 default "7" if MIPS_L1_CACHE_SHIFT_7
401 default "6" if MIPS_L1_CACHE_SHIFT_6
402 default "5" if MIPS_L1_CACHE_SHIFT_5
403 default "4" if MIPS_L1_CACHE_SHIFT_4
409 Select this if your system includes an L2 cache and you want U-Boot
410 to initialise & maintain it.
412 config DYNAMIC_IO_PORT_BASE
418 Select this if your system contains a MIPS Coherence Manager and you
419 wish U-Boot to configure it or make use of it to retrieve system
420 information such as cache configuration.
422 config MIPS_INSERT_BOOT_CONFIG
426 Enable this to insert some board-specific boot configuration in
427 the U-Boot binary at offset 0x10.
429 config MIPS_BOOT_CONFIG_WORD0
431 depends on MIPS_INSERT_BOOT_CONFIG
432 default 0x420 if TARGET_MALTA
435 Value which is inserted as boot config word 0.
437 config MIPS_BOOT_CONFIG_WORD1
439 depends on MIPS_INSERT_BOOT_CONFIG
442 Value which is inserted as boot config word 1.