rockchip: px5: enable spl-fifo-mode for emmc for px5-evb
[oweals/u-boot.git] / arch / microblaze / cpu / timer.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2007 Michal Simek
4  *
5  * Michal  SIMEK <monstr@monstr.eu>
6  */
7
8 #include <common.h>
9 #include <fdtdec.h>
10 #include <time.h>
11 #include <asm/microblaze_timer.h>
12 #include <asm/microblaze_intc.h>
13
14 DECLARE_GLOBAL_DATA_PTR;
15
16 volatile int timestamp = 0;
17 microblaze_timer_t *tmr;
18
19 ulong get_timer (ulong base)
20 {
21         if (tmr)
22                 return timestamp - base;
23         return timestamp++ - base;
24 }
25
26 void __udelay(unsigned long usec)
27 {
28         u32 i;
29
30         if (tmr) {
31                 i = get_timer(0);
32                 while ((get_timer(0) - i) < (usec / 1000))
33                         ;
34         }
35 }
36
37 #ifndef CONFIG_SPL_BUILD
38 static void timer_isr(void *arg)
39 {
40         timestamp++;
41         tmr->control = tmr->control | TIMER_INTERRUPT;
42 }
43
44 int timer_init (void)
45 {
46         int irq = -1;
47         u32 preload = 0;
48         u32 ret = 0;
49         const void *blob = gd->fdt_blob;
50         int node = 0;
51         u32 cell[2];
52
53         debug("TIMER: Initialization\n");
54
55         /* Do not init before relocation */
56         if (!(gd->flags & GD_FLG_RELOC))
57                 return 0;
58
59         node = fdt_node_offset_by_compatible(blob, node,
60                                 "xlnx,xps-timer-1.00.a");
61         if (node != -1) {
62                 fdt_addr_t base = fdtdec_get_addr(blob, node, "reg");
63                 if (base == FDT_ADDR_T_NONE)
64                         return -1;
65
66                 debug("TIMER: Base addr %lx\n", base);
67                 tmr = (microblaze_timer_t *)base;
68
69                 ret = fdtdec_get_int_array(blob, node, "interrupts",
70                                             cell, ARRAY_SIZE(cell));
71                 if (ret)
72                         return ret;
73
74                 irq = cell[0];
75                 debug("TIMER: IRQ %x\n", irq);
76
77                 preload = fdtdec_get_int(blob, node, "clock-frequency", 0);
78                 preload /= CONFIG_SYS_HZ;
79         } else {
80                 return node;
81         }
82
83         if (tmr && preload && irq >= 0) {
84                 tmr->loadreg = preload;
85                 tmr->control = TIMER_INTERRUPT | TIMER_RESET;
86                 tmr->control = TIMER_ENABLE | TIMER_ENABLE_INTR |\
87                                         TIMER_RELOAD | TIMER_DOWN_COUNT;
88                 timestamp = 0;
89                 ret = install_interrupt_handler (irq, timer_isr, (void *)tmr);
90                 if (ret)
91                         tmr = NULL;
92         }
93         /* No problem if timer is not found/initialized */
94         return 0;
95 }
96 #else
97 int timer_init(void)
98 {
99         return 0;
100 }
101 #endif
102
103 /*
104  * This function is derived from PowerPC code (read timebase as long long).
105  * On Microblaze it just returns the timer value.
106  */
107 unsigned long long get_ticks(void)
108 {
109         return get_timer(0);
110 }
111
112 /*
113  * This function is derived from PowerPC code (timebase clock frequency).
114  * On Microblaze it returns the number of timer ticks per second.
115  */
116 ulong get_tbclk(void)
117 {
118         return CONFIG_SYS_HZ;
119 }