2 * (C) Copyright 2007 Michal Simek
3 * (C) Copyright 2004 Atmark Techno, Inc.
5 * Michal SIMEK <monstr@monstr.eu>
6 * Yasushi SHOJI <yashi@atmark-techno.com>
8 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm-offsets.h>
19 * r10: Stores little/big endian offset for vectors
20 * r2: Stores imm opcode
21 * r3: Stores brai opcode
24 mts rmsr, r0 /* disable cache */
25 addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
26 addi r1, r1, -4 /* Decrement SP to top of memory */
28 /* Find-out if u-boot is running on BIG/LITTLE endian platform
29 * There are some steps which is necessary to keep in mind:
30 * 1. Setup offset value to r6
31 * 2. Store word offset value to address 0x0
32 * 3. Load just byte from address 0x0
33 * 4a) LITTLE endian - r10 contains 0x2 because it is the smallest
34 * value that's why is on address 0x0
35 * 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
37 addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
39 swi r6, r0, 0x28 /* used first unused MB vector */
40 lbui r10, r0, 0x28 /* used first unused MB vector */
43 /* add opcode instruction for 32bit jump - 2 instruction imm & brai */
44 addi r2, r0, 0xb0000000 /* hex b000 opcode imm */
45 addi r3, r0, 0xb8080000 /* hew b808 opcode brai */
47 #ifdef CONFIG_SYS_RESET_ADDRESS
49 swi r2, r0, 0x0 /* reset address - imm opcode */
50 swi r3, r0, 0x4 /* reset address - brai opcode */
52 addik r6, r0, CONFIG_SYS_RESET_ADDRESS
61 #ifdef CONFIG_SYS_USR_EXCEP
62 /* user_vector_exception */
63 swi r2, r0, 0x8 /* user vector exception - imm opcode */
64 swi r3, r0, 0xC /* user vector exception - brai opcode */
66 addik r6, r0, _exception_handler
69 * BIG ENDIAN memory map for user exception
73 * then it is necessary to count address for storing the most significant
74 * 16bits from _exception_handler address and copy it to
75 * 0xa address. Big endian use offset in r10=0 that's why is it just
76 * 0xa address. The same is done for the least significant 16 bits
79 * LITTLE ENDIAN memory map for user exception
83 * Offset is for little endian setup to 0x2. rsubi instruction decrease
84 * address value to ensure that points to proper place which is
85 * 0x8 for the most significant 16 bits and
86 * 0xC for the least significant 16 bits
95 /* interrupt_handler */
96 swi r2, r0, 0x10 /* interrupt - imm opcode */
97 swi r3, r0, 0x14 /* interrupt - brai opcode */
99 addik r6, r0, _interrupt_handler
107 /* hardware exception */
108 swi r2, r0, 0x20 /* hardware exception - imm opcode */
109 swi r3, r0, 0x24 /* hardware exception - brai opcode */
111 addik r6, r0, _hw_exception_handler
119 /* Flush cache before enable cache */
121 addik r6, r0, XILINX_DCACHE_BYTE_SIZE
122 flush: bralid r15, flush_cache
125 /* enable instruction and data cache */
131 /* clear BSS segments */
132 addi r5, r0, __bss_start
133 addi r4, r0, __bss_end
137 swi r0, r5, 0 /* write zero to loc */
138 addi r5, r5, 4 /* increment to next loc */
139 cmp r6, r5, r4 /* check if we have reach the end */
141 3: /* jumping to board_init */
146 * Read 16bit little endian
162 * Write 16bit little endian
163 * first parameter(r5) - address, second(r6) - short value
169 out16: bslli r3, r6, 8