1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * MCF5441x Internal Memory Map
5 * Copyright 2010-2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 #ifndef __IMMAP_5441X__
10 #define __IMMAP_5441X__
12 /* Module Base Addresses */
13 #define MMAP_XBS 0xFC004000
14 #define MMAP_FBCS 0xFC008000
15 #define MMAP_CAN0 0xFC020000
16 #define MMAP_CAN1 0xFC024000
17 #define MMAP_I2C1 0xFC038000
18 #define MMAP_DSPI1 0xFC03C000
19 #define MMAP_SCM 0xFC040000
20 #define MMAP_PM 0xFC04002C
21 #define MMAP_EDMA 0xFC044000
22 #define MMAP_INTC0 0xFC048000
23 #define MMAP_INTC1 0xFC04C000
24 #define MMAP_INTC2 0xFC050000
25 #define MMAP_IACK 0xFC054000
26 #define MMAP_I2C0 0xFC058000
27 #define MMAP_DSPI0 0xFC05C000
28 #define MMAP_UART0 0xFC060000
29 #define MMAP_UART1 0xFC064000
30 #define MMAP_UART2 0xFC068000
31 #define MMAP_UART3 0xFC06C000
32 #define MMAP_DTMR0 0xFC070000
33 #define MMAP_DTMR1 0xFC074000
34 #define MMAP_DTMR2 0xFC078000
35 #define MMAP_DTMR3 0xFC07C000
36 #define MMAP_PIT0 0xFC080000
37 #define MMAP_PIT1 0xFC084000
38 #define MMAP_PIT2 0xFC088000
39 #define MMAP_PIT3 0xFC08C000
40 #define MMAP_EPORT0 0xFC090000
41 #define MMAP_ADC 0xFC094000
42 #define MMAP_DAC0 0xFC098000
43 #define MMAP_DAC1 0xFC09C000
44 #define MMAP_RRTC 0xFC0A8000
45 #define MMAP_SIM 0xFC0AC000
46 #define MMAP_USBOTG 0xFC0B0000
47 #define MMAP_USBEHCI 0xFC0B4000
48 #define MMAP_SDRAM 0xFC0B8000
49 #define MMAP_SSI0 0xFC0BC000
50 #define MMAP_PLL 0xFC0C0000
51 #define MMAP_RNG 0xFC0C4000
52 #define MMAP_SSI1 0xFC0C8000
53 #define MMAP_ESDHC 0xFC0CC000
54 #define MMAP_FEC0 0xFC0D4000
55 #define MMAP_FEC1 0xFC0D8000
56 #define MMAP_L2_SW0 0xFC0DC000
57 #define MMAP_L2_SW1 0xFC0E0000
59 #define MMAP_NFC_RAM 0xFC0FC000
60 #define MMAP_NFC 0xFC0FF000
62 #define MMAP_1WIRE 0xEC008000
63 #define MMAP_I2C2 0xEC010000
64 #define MMAP_I2C3 0xEC014000
65 #define MMAP_I2C4 0xEC018000
66 #define MMAP_I2C5 0xEC01C000
67 #define MMAP_DSPI2 0xEC038000
68 #define MMAP_DSPI3 0xEC03C000
69 #define MMAP_UART4 0xEC060000
70 #define MMAP_UART5 0xEC064000
71 #define MMAP_UART6 0xEC068000
72 #define MMAP_UART7 0xEC06C000
73 #define MMAP_UART8 0xEC070000
74 #define MMAP_UART9 0xEC074000
75 #define MMAP_RCM 0xEC090000
76 #define MMAP_CCM 0xEC090000
77 #define MMAP_GPIO 0xEC094000
79 #include <asm/coldfire/crossbar.h>
80 #include <asm/coldfire/dspi.h>
81 #include <asm/coldfire/edma.h>
82 #include <asm/coldfire/eport.h>
83 #include <asm/coldfire/flexbus.h>
84 #include <asm/coldfire/flexcan.h>
85 #include <asm/coldfire/intctrl.h>
86 #include <asm/coldfire/ssi.h>
88 /* Serial Boot Facility (SBF) */
91 u16 sbfsr; /* Serial Boot Facility Status */
93 u16 sbfcr; /* Serial Boot Facility Control */
96 /* Reset Controller Module (RCM) */
102 /* Chip Configuration Module (CCM) */
104 u8 ccm_resv0[0x4]; /* 0x00 */
105 u16 ccr; /* 0x04 Chip Configuration */
106 u8 resv1[0x2]; /* 0x06 */
107 u16 rcon; /* 0x08 Reset Configuration */
108 u16 cir; /* 0x0A Chip Identification */
109 u8 resv2[0x2]; /* 0x0C */
110 u16 misccr; /* 0x0E Miscellaneous Control */
111 u16 cdrh; /* 0x10 Clock Divider */
112 u16 cdrl; /* 0x12 Clock Divider */
113 u16 uocsr; /* 0x14 USB On-the-Go Controller Status */
114 u16 uhcsr; /* 0x16 */
115 u16 misccr3; /* 0x18 */
116 u16 misccr2; /* 0x1A */
117 u16 adctsr; /* 0x1C */
118 u16 dactsr; /* 0x1E */
119 u16 sbfsr; /* 0x20 */
120 u16 sbfcr; /* 0x22 */
121 u32 fnacr; /* 0x24 */
124 /* General Purpose I/O Module (GPIO) */
125 typedef struct gpio {
126 u8 podr_a; /* 0x00 */
127 u8 podr_b; /* 0x01 */
128 u8 podr_c; /* 0x02 */
129 u8 podr_d; /* 0x03 */
130 u8 podr_e; /* 0x04 */
131 u8 podr_f; /* 0x05 */
132 u8 podr_g; /* 0x06 */
133 u8 podr_h; /* 0x07 */
134 u8 podr_i; /* 0x08 */
135 u8 podr_j; /* 0x09 */
136 u8 podr_k; /* 0x0A */
139 u8 pddr_a; /* 0x0C */
140 u8 pddr_b; /* 0x0D */
141 u8 pddr_c; /* 0x0E */
142 u8 pddr_d; /* 0x0F */
143 u8 pddr_e; /* 0x10 */
144 u8 pddr_f; /* 0x11 */
145 u8 pddr_g; /* 0x12 */
146 u8 pddr_h; /* 0x13 */
147 u8 pddr_i; /* 0x14 */
148 u8 pddr_j; /* 0x15 */
149 u8 pddr_k; /* 0x16 */
152 u8 ppdsdr_a; /* 0x18 */
153 u8 ppdsdr_b; /* 0x19 */
154 u8 ppdsdr_c; /* 0x1A */
155 u8 ppdsdr_d; /* 0x1B */
156 u8 ppdsdr_e; /* 0x1C */
157 u8 ppdsdr_f; /* 0x1D */
158 u8 ppdsdr_g; /* 0x1E */
159 u8 ppdsdr_h; /* 0x1F */
160 u8 ppdsdr_i; /* 0x20 */
161 u8 ppdsdr_j; /* 0x21 */
162 u8 ppdsdr_k; /* 0x22 */
165 u8 pclrr_a; /* 0x24 */
166 u8 pclrr_b; /* 0x25 */
167 u8 pclrr_c; /* 0x26 */
168 u8 pclrr_d; /* 0x27 */
169 u8 pclrr_e; /* 0x28 */
170 u8 pclrr_f; /* 0x29 */
171 u8 pclrr_g; /* 0x2A */
172 u8 pclrr_h; /* 0x2B */
173 u8 pclrr_i; /* 0x2C */
174 u8 pclrr_j; /* 0x2D */
175 u8 pclrr_k; /* 0x2E */
178 u16 pcr_a; /* 0x30 */
179 u16 pcr_b; /* 0x32 */
180 u16 pcr_c; /* 0x34 */
181 u16 pcr_d; /* 0x36 */
182 u16 pcr_e; /* 0x38 */
183 u16 pcr_f; /* 0x3A */
184 u16 pcr_g; /* 0x3C */
185 u16 pcr_h; /* 0x3E */
186 u16 pcr_i; /* 0x40 */
187 u16 pcr_j; /* 0x42 */
188 u16 pcr_k; /* 0x44 */
189 u16 rsvd4; /* 0x46 */
191 u8 par_fbctl; /* 0x48 */
192 u8 par_be; /* 0x49 */
193 u8 par_cs; /* 0x4A */
194 u8 par_cani2c; /* 0x4B */
195 u8 par_irqh; /* 0x4C */
196 u8 par_irql; /* 0x4D */
197 u8 par_dspi0; /* 0x4E */
198 u8 par_dspiow; /* 0x4F */
199 u8 par_timer; /* 0x50 */
200 u8 par_uart2; /* 0x51 */
201 u8 par_uart1; /* 0x52 */
202 u8 par_uart0; /* 0x53 */
203 u8 par_sdhch; /* 0x54 */
204 u8 par_sdhcl; /* 0x55 */
205 u8 par_simp0h; /* 0x56 */
206 u8 par_simp1h; /* 0x57 */
207 u8 par_ssi0h; /* 0x58 */
208 u8 par_ssi0l; /* 0x59 */
209 u8 par_dbg1h; /* 0x5A */
210 u8 par_dbg0h; /* 0x5B */
211 u8 par_dbgl; /* 0x5C */
213 u8 par_fec; /* 0x5E */
216 u8 mscr_sdram; /* 0x60 */
217 u8 rsvd7[3]; /* 0x61-0x63 */
219 u8 srcr_fb1; /* 0x64 */
220 u8 srcr_fb2; /* 0x65 */
221 u8 srcr_fb3; /* 0x66 */
222 u8 srcr_fb4; /* 0x67 */
223 u8 srcr_dspiow; /* 0x68 */
224 u8 srcr_cani2c; /* 0x69 */
225 u8 srcr_irq; /* 0x6A */
226 u8 srcr_timer; /* 0x6B */
227 u8 srcr_uart; /* 0x6C */
228 u8 srcr_fec; /* 0x6D */
229 u8 srcr_sdhc; /* 0x6E */
230 u8 srcr_simp0; /* 0x6F */
231 u8 srcr_ssi0; /* 0x70 */
232 u8 rsvd8[3]; /* 0x71-0x73 */
234 u16 urts_pol; /* 0x74 */
235 u16 ucts_pol; /* 0x76 */
236 u16 utxd_wom; /* 0x78 */
237 u32 urxd_wom; /* 0x7c */
243 /* SDRAM Controller (SDRAMC) */
244 typedef struct sdramc {
315 u32 rsvd3[32]; /* 0xF4-0x1A8 */
317 u32 rcrcr; /* 0x180 */
318 u32 swrcr; /* 0x184 */
320 u32 msovr; /* 0x18C */
321 u32 rcrdbg; /* 0x190 */
322 u32 sl0adj; /* 0x194 */
323 u32 sl1adj; /* 0x198 */
324 u32 sl2adj; /* 0x19C */
325 u32 sl3adj; /* 0x1A0 */
326 u32 sl4adj; /* 0x1A4 */
327 u32 flight_tm; /* 0x1A8 */
328 u32 padcr; /* 0x1AC */
331 /* Phase Locked Loop (PLL) */
333 u32 pcr; /* Control */
334 u32 pdr; /* Divider */
335 u32 psr; /* Status */
339 u8 rsvd1[19]; /* 0x00 - 0x12 */
341 u16 rsvd2; /* 0x14 - 0x15 */
343 u8 rsvd3[3]; /* 0x18 - 0x1A */
345 u8 rsvd4[3]; /* 0x1C - 0x1E */
346 u8 scmisr; /* 0x1F */
347 u32 rsvd5; /* 0x20 - 0x23 */
349 u8 rsvd6[72]; /* 0x28 - 0x6F */
350 u32 cfadr; /* 0x70 */
355 u32 rsvd8; /* 0x78 - 0x7B */
356 u32 cfdtr; /* 0x7C */
370 #endif /* __IMMAP_5441X__ */