2 * MCF5441x Internal Memory Map
4 * Copyright 2010-2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #ifndef __IMMAP_5441X__
27 #define __IMMAP_5441X__
29 /* Module Base Addresses */
30 #define MMAP_XBS 0xFC004000
31 #define MMAP_FBCS 0xFC008000
32 #define MMAP_CAN0 0xFC020000
33 #define MMAP_CAN1 0xFC024000
34 #define MMAP_I2C1 0xFC038000
35 #define MMAP_DSPI1 0xFC03C000
36 #define MMAP_SCM 0xFC040000
37 #define MMAP_PM 0xFC04002C
38 #define MMAP_EDMA 0xFC044000
39 #define MMAP_INTC0 0xFC048000
40 #define MMAP_INTC1 0xFC04C000
41 #define MMAP_INTC2 0xFC050000
42 #define MMAP_IACK 0xFC054000
43 #define MMAP_I2C0 0xFC058000
44 #define MMAP_DSPI0 0xFC05C000
45 #define MMAP_UART0 0xFC060000
46 #define MMAP_UART1 0xFC064000
47 #define MMAP_UART2 0xFC068000
48 #define MMAP_UART3 0xFC06C000
49 #define MMAP_DTMR0 0xFC070000
50 #define MMAP_DTMR1 0xFC074000
51 #define MMAP_DTMR2 0xFC078000
52 #define MMAP_DTMR3 0xFC07C000
53 #define MMAP_PIT0 0xFC080000
54 #define MMAP_PIT1 0xFC084000
55 #define MMAP_PIT2 0xFC088000
56 #define MMAP_PIT3 0xFC08C000
57 #define MMAP_EPORT0 0xFC090000
58 #define MMAP_ADC 0xFC094000
59 #define MMAP_DAC0 0xFC098000
60 #define MMAP_DAC1 0xFC09C000
61 #define MMAP_RRTC 0xFC0A8000
62 #define MMAP_SIM 0xFC0AC000
63 #define MMAP_USBOTG 0xFC0B0000
64 #define MMAP_USBEHCI 0xFC0B4000
65 #define MMAP_SDRAM 0xFC0B8000
66 #define MMAP_SSI0 0xFC0BC000
67 #define MMAP_PLL 0xFC0C0000
68 #define MMAP_RNG 0xFC0C4000
69 #define MMAP_SSI1 0xFC0C8000
70 #define MMAP_ESDHC 0xFC0CC000
71 #define MMAP_FEC0 0xFC0D4000
72 #define MMAP_FEC1 0xFC0D8000
73 #define MMAP_L2_SW0 0xFC0DC000
74 #define MMAP_L2_SW1 0xFC0E0000
76 #define MMAP_NFC_RAM 0xFC0FC000
77 #define MMAP_NFC 0xFC0FF000
79 #define MMAP_1WIRE 0xEC008000
80 #define MMAP_I2C2 0xEC010000
81 #define MMAP_I2C3 0xEC014000
82 #define MMAP_I2C4 0xEC018000
83 #define MMAP_I2C5 0xEC01C000
84 #define MMAP_DSPI2 0xEC038000
85 #define MMAP_DSPI3 0xEC03C000
86 #define MMAP_UART4 0xEC060000
87 #define MMAP_UART5 0xEC064000
88 #define MMAP_UART6 0xEC068000
89 #define MMAP_UART7 0xEC06C000
90 #define MMAP_UART8 0xEC070000
91 #define MMAP_UART9 0xEC074000
92 #define MMAP_RCM 0xEC090000
93 #define MMAP_CCM 0xEC090000
94 #define MMAP_GPIO 0xEC094000
96 #include <asm/coldfire/crossbar.h>
97 #include <asm/coldfire/dspi.h>
98 #include <asm/coldfire/edma.h>
99 #include <asm/coldfire/eport.h>
100 #include <asm/coldfire/flexbus.h>
101 #include <asm/coldfire/flexcan.h>
102 #include <asm/coldfire/intctrl.h>
103 #include <asm/coldfire/ssi.h>
105 /* Serial Boot Facility (SBF) */
108 u16 sbfsr; /* Serial Boot Facility Status */
110 u16 sbfcr; /* Serial Boot Facility Control */
113 /* Reset Controller Module (RCM) */
119 /* Chip Configuration Module (CCM) */
121 u8 ccm_resv0[0x4]; /* 0x00 */
122 u16 ccr; /* 0x04 Chip Configuration */
123 u8 resv1[0x2]; /* 0x06 */
124 u16 rcon; /* 0x08 Reset Configuration */
125 u16 cir; /* 0x0A Chip Identification */
126 u8 resv2[0x2]; /* 0x0C */
127 u16 misccr; /* 0x0E Miscellaneous Control */
128 u16 cdrh; /* 0x10 Clock Divider */
129 u16 cdrl; /* 0x12 Clock Divider */
130 u16 uocsr; /* 0x14 USB On-the-Go Controller Status */
131 u16 uhcsr; /* 0x16 */
132 u16 misccr3; /* 0x18 */
133 u16 misccr2; /* 0x1A */
134 u16 adctsr; /* 0x1C */
135 u16 dactsr; /* 0x1E */
136 u16 sbfsr; /* 0x20 */
137 u16 sbfcr; /* 0x22 */
138 u32 fnacr; /* 0x24 */
141 /* General Purpose I/O Module (GPIO) */
142 typedef struct gpio {
143 u8 podr_a; /* 0x00 */
144 u8 podr_b; /* 0x01 */
145 u8 podr_c; /* 0x02 */
146 u8 podr_d; /* 0x03 */
147 u8 podr_e; /* 0x04 */
148 u8 podr_f; /* 0x05 */
149 u8 podr_g; /* 0x06 */
150 u8 podr_h; /* 0x07 */
151 u8 podr_i; /* 0x08 */
152 u8 podr_j; /* 0x09 */
153 u8 podr_k; /* 0x0A */
156 u8 pddr_a; /* 0x0C */
157 u8 pddr_b; /* 0x0D */
158 u8 pddr_c; /* 0x0E */
159 u8 pddr_d; /* 0x0F */
160 u8 pddr_e; /* 0x10 */
161 u8 pddr_f; /* 0x11 */
162 u8 pddr_g; /* 0x12 */
163 u8 pddr_h; /* 0x13 */
164 u8 pddr_i; /* 0x14 */
165 u8 pddr_j; /* 0x15 */
166 u8 pddr_k; /* 0x16 */
169 u8 ppdsdr_a; /* 0x18 */
170 u8 ppdsdr_b; /* 0x19 */
171 u8 ppdsdr_c; /* 0x1A */
172 u8 ppdsdr_d; /* 0x1B */
173 u8 ppdsdr_e; /* 0x1C */
174 u8 ppdsdr_f; /* 0x1D */
175 u8 ppdsdr_g; /* 0x1E */
176 u8 ppdsdr_h; /* 0x1F */
177 u8 ppdsdr_i; /* 0x20 */
178 u8 ppdsdr_j; /* 0x21 */
179 u8 ppdsdr_k; /* 0x22 */
182 u8 pclrr_a; /* 0x24 */
183 u8 pclrr_b; /* 0x25 */
184 u8 pclrr_c; /* 0x26 */
185 u8 pclrr_d; /* 0x27 */
186 u8 pclrr_e; /* 0x28 */
187 u8 pclrr_f; /* 0x29 */
188 u8 pclrr_g; /* 0x2A */
189 u8 pclrr_h; /* 0x2B */
190 u8 pclrr_i; /* 0x2C */
191 u8 pclrr_j; /* 0x2D */
192 u8 pclrr_k; /* 0x2E */
195 u16 pcr_a; /* 0x30 */
196 u16 pcr_b; /* 0x32 */
197 u16 pcr_c; /* 0x34 */
198 u16 pcr_d; /* 0x36 */
199 u16 pcr_e; /* 0x38 */
200 u16 pcr_f; /* 0x3A */
201 u16 pcr_g; /* 0x3C */
202 u16 pcr_h; /* 0x3E */
203 u16 pcr_i; /* 0x40 */
204 u16 pcr_j; /* 0x42 */
205 u16 pcr_k; /* 0x44 */
206 u16 rsvd4; /* 0x46 */
208 u8 par_fbctl; /* 0x48 */
209 u8 par_be; /* 0x49 */
210 u8 par_cs; /* 0x4A */
211 u8 par_cani2c; /* 0x4B */
212 u8 par_irqh; /* 0x4C */
213 u8 par_irql; /* 0x4D */
214 u8 par_dspi0; /* 0x4E */
215 u8 par_dspiow; /* 0x4F */
216 u8 par_timer; /* 0x50 */
217 u8 par_uart2; /* 0x51 */
218 u8 par_uart1; /* 0x52 */
219 u8 par_uart0; /* 0x53 */
220 u8 par_sdhch; /* 0x54 */
221 u8 par_sdhcl; /* 0x55 */
222 u8 par_simp0h; /* 0x56 */
223 u8 par_simp1h; /* 0x57 */
224 u8 par_ssi0h; /* 0x58 */
225 u8 par_ssi0l; /* 0x59 */
226 u8 par_dbg1h; /* 0x5A */
227 u8 par_dbg0h; /* 0x5B */
228 u8 par_dbgl; /* 0x5C */
230 u8 par_fec; /* 0x5E */
233 u8 mscr_sdram; /* 0x60 */
234 u8 rsvd7[3]; /* 0x61-0x63 */
236 u8 srcr_fb1; /* 0x64 */
237 u8 srcr_fb2; /* 0x65 */
238 u8 srcr_fb3; /* 0x66 */
239 u8 srcr_fb4; /* 0x67 */
240 u8 srcr_dspiow; /* 0x68 */
241 u8 srcr_cani2c; /* 0x69 */
242 u8 srcr_irq; /* 0x6A */
243 u8 srcr_timer; /* 0x6B */
244 u8 srcr_uart; /* 0x6C */
245 u8 srcr_fec; /* 0x6D */
246 u8 srcr_sdhc; /* 0x6E */
247 u8 srcr_simp0; /* 0x6F */
248 u8 srcr_ssi0; /* 0x70 */
249 u8 rsvd8[3]; /* 0x71-0x73 */
251 u16 urts_pol; /* 0x74 */
252 u16 ucts_pol; /* 0x76 */
253 u16 utxd_wom; /* 0x78 */
254 u32 urxd_wom; /* 0x7c */
260 /* SDRAM Controller (SDRAMC) */
261 typedef struct sdramc {
332 u32 rsvd3[32]; /* 0xF4-0x1A8 */
334 u32 rcrcr; /* 0x180 */
335 u32 swrcr; /* 0x184 */
337 u32 msovr; /* 0x18C */
338 u32 rcrdbg; /* 0x190 */
339 u32 sl0adj; /* 0x194 */
340 u32 sl1adj; /* 0x198 */
341 u32 sl2adj; /* 0x19C */
342 u32 sl3adj; /* 0x1A0 */
343 u32 sl4adj; /* 0x1A4 */
344 u32 flight_tm; /* 0x1A8 */
345 u32 padcr; /* 0x1AC */
348 /* Phase Locked Loop (PLL) */
350 u32 pcr; /* Control */
351 u32 pdr; /* Divider */
352 u32 psr; /* Status */
356 u8 rsvd1[19]; /* 0x00 - 0x12 */
358 u16 rsvd2; /* 0x14 - 0x15 */
360 u8 rsvd3[3]; /* 0x18 - 0x1A */
362 u8 rsvd4[3]; /* 0x1C - 0x1E */
363 u8 scmisr; /* 0x1F */
364 u32 rsvd5; /* 0x20 - 0x23 */
366 u8 rsvd6[72]; /* 0x28 - 0x6F */
367 u32 cfadr; /* 0x70 */
372 u32 rsvd8; /* 0x78 - 0x7B */
373 u32 cfdtr; /* 0x7C */
387 #endif /* __IMMAP_5441X__ */