1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * MCF520x Internal Memory Map
5 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 #define __IMMAP_520X__
12 #define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
13 #define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
14 #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
15 #define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000)
16 #define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000)
17 #define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
18 #define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
19 #define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000)
20 #define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000)
21 #define MMAP_QSPI (CONFIG_SYS_MBAR + 0x0005C000)
22 #define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000)
23 #define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000)
24 #define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000)
25 #define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000)
26 #define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000)
27 #define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000)
28 #define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000)
29 #define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000)
30 #define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000)
31 #define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00088000)
32 #define MMAP_WDOG (CONFIG_SYS_MBAR + 0x0008C000)
33 #define MMAP_PLL (CONFIG_SYS_MBAR + 0x00090000)
34 #define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000)
35 #define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004)
36 #define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000)
37 #define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000A8000)
39 #include <asm/coldfire/crossbar.h>
40 #include <asm/coldfire/edma.h>
41 #include <asm/coldfire/eport.h>
42 #include <asm/coldfire/flexbus.h>
43 #include <asm/coldfire/intctrl.h>
44 #include <asm/coldfire/qspi.h>
46 /* System Controller Module */
48 u32 mpr; /* 0x00 Master Privilege */
50 u32 pacra; /* 0x20 Peripheral Access Ctrl A */
51 u32 pacrb; /* 0x24 Peripheral Access Ctrl B */
52 u32 pacrc; /* 0x28 Peripheral Access Ctrl C */
53 u32 pacrd; /* 0x2C Peripheral Access Ctrl D */
55 u32 pacre; /* 0x40 Peripheral Access Ctrl E */
56 u32 pacrf; /* 0x44 Peripheral Access Ctrl F */
58 u32 bmt; /* 0x50 bus monitor */
62 u8 rsvd1[19]; /* 0x00 - 0x12 */
64 u16 rsvd2; /* 0x14 - 0x15 */
66 u8 rsvd3[3]; /* 0x18 - 0x1A */
68 u8 rsvd4[3]; /* 0x1C - 0x1E */
70 u8 rsvd5[79]; /* 0x20 - 0x6F */
76 u32 rsvd8; /* 0x78 - 0x7B */
80 /* Chip configuration module */
86 typedef struct ccm_ctrl {
87 u16 ccr; /* 0x00 Chip Cfg */
89 u16 rcon; /* 0x04 Reset Cfg */
90 u16 cir; /* 0x06 Chip ID */
94 typedef struct gpio_ctrl {
95 /* Port Output Data */
96 u8 podr_busctl; /* 0x00 */
97 u8 podr_be; /* 0x01 */
98 u8 podr_cs; /* 0x02 */
99 u8 podr_feci2c; /* 0x03 */
100 u8 podr_qspi; /* 0x04 */
101 u8 podr_timer; /* 0x05 */
102 u8 podr_uart; /* 0x06 */
103 u8 podr_fech; /* 0x07 */
104 u8 podr_fecl; /* 0x08 */
105 u8 res01[3]; /* 0x9 - 0x0B */
107 /* Port Data Direction */
108 u8 pddr_busctl; /* 0x0C */
109 u8 pddr_be; /* 0x0D */
110 u8 pddr_cs; /* 0x0E */
111 u8 pddr_feci2c; /* 0x0F */
112 u8 pddr_qspi; /* 0x10*/
113 u8 pddr_timer; /* 0x11 */
114 u8 pddr_uart; /* 0x12 */
115 u8 pddr_fech; /* 0x13 */
116 u8 pddr_fecl; /* 0x14 */
117 u8 res02[5]; /* 0x15 - 0x19 */
119 /* Port Data Direction */
120 u8 ppdr_cs; /* 0x1A */
121 u8 ppdr_feci2c; /* 0x1B */
122 u8 ppdr_qspi; /* 0x1C */
123 u8 ppdr_timer; /* 0x1D */
124 u8 ppdr_uart; /* 0x1E */
125 u8 ppdr_fech; /* 0x1F */
126 u8 ppdr_fecl; /* 0x20 */
127 u8 res03[3]; /* 0x21 - 0x23 */
129 /* Port Clear Output Data */
130 u8 pclrr_busctl; /* 0x24 */
131 u8 pclrr_be; /* 0x25 */
132 u8 pclrr_cs; /* 0x26 */
133 u8 pclrr_feci2c; /* 0x27 */
134 u8 pclrr_qspi; /* 0x28 */
135 u8 pclrr_timer; /* 0x29 */
136 u8 pclrr_uart; /* 0x2A */
137 u8 pclrr_fech; /* 0x2B */
138 u8 pclrr_fecl; /* 0x2C */
139 u8 res04[3]; /* 0x2D - 0x2F */
142 u8 par_busctl; /* 0x30 */
143 u8 par_be; /* 0x31 */
144 u8 par_cs; /* 0x32 */
145 u8 par_feci2c; /* 0x33 */
146 u8 par_qspi; /* 0x34 */
147 u8 par_timer; /* 0x35 */
148 u16 par_uart; /* 0x36 */
149 u8 par_fec; /* 0x38 */
150 u8 par_irq; /* 0x39 */
152 /* Mode Select Control */
153 /* Drive Strength Control */
154 u8 mscr_fb; /* 0x3A */
155 u8 mscr_sdram; /* 0x3B */
157 u8 dscr_i2c; /* 0x3C */
158 u8 dscr_misc; /* 0x3D */
159 u8 dscr_fec; /* 0x3E */
160 u8 dscr_uart; /* 0x3F */
161 u8 dscr_qspi; /* 0x40 */
164 /* SDRAM controller */
165 typedef struct sdram_ctrl {
166 u32 mode; /* 0x00 Mode/Extended Mode */
167 u32 ctrl; /* 0x04 Ctrl */
168 u32 cfg1; /* 0x08 Cfg 1 */
169 u32 cfg2; /* 0x0C Cfg 2 */
170 u32 res1[64]; /* 0x10 - 0x10F */
171 u32 cs0; /* 0x110 Chip Select 0 Cfg */
172 u32 cs1; /* 0x114 Chip Select 1 Cfg */
176 typedef struct pll_ctrl {
177 u8 odr; /* 0x00 Output divider */
179 u8 cr; /* 0x02 Control */
181 u8 mdr; /* 0x04 Modulation Divider */
183 u8 fdr; /* 0x06 Feedback Divider */
187 /* Watchdog registers */
188 typedef struct wdog_ctrl {
189 u16 cr; /* 0x00 Control */
190 u16 mr; /* 0x02 Modulus */
191 u16 cntr; /* 0x04 Count */
192 u16 sr; /* 0x06 Service */
195 #endif /* __IMMAP_520X__ */