1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * fsl_mcdmafec.h -- Multi-channel DMA Fast Ethernet Controller definitions
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 #define fsl_mcdmafec_h
12 /* Re-use of the definitions */
15 typedef struct fecdma {
16 u32 rsvd0; /* 0x000 */
19 u32 rsvd1[6]; /* 0x00C - 0x023 */
21 u32 rsvd2[6]; /* 0x028 - 0x03F */
24 u32 rsvd3[7]; /* 0x048 - 0x063 */
26 u32 rsvd4[7]; /* 0x068 - 0x083 */
29 u32 rsvd5[14]; /* 0x08C - 0x0C3 */
31 u32 rsvd6[7]; /* 0x0C8 - 0x0E3 */
35 u32 rsvd7[10]; /* 0x0F0 - 0x117 */
40 u32 rsvd8[7]; /* 0x128 - 0x143 */
42 u32 rsvd9[14]; /* 0x148 - 0x17F */
47 u32 rlrfp; /* 0x190 */
48 u32 rlwfp; /* 0x194 */
55 u32 tlrfp; /* 0x1B0 */
56 u32 tlwfp; /* 0x1B4 */
61 u32 ctcwr; /* 0x1C8 */
73 cbd_t *rxbd; /* Rx BD */
74 cbd_t *txbd; /* Tx BD */
79 struct fec_info_dma *next;
80 u16 rx_task; /* DMA receive Task Number */
81 u16 tx_task; /* DMA Transmit Task Number */
82 u16 rx_pri; /* DMA Receive Priority */
83 u16 tx_pri; /* DMA Transmit Priority */
84 u16 rx_init; /* DMA Receive Initiator */
85 u16 tx_init; /* DMA Transmit Initiator */
86 u16 used_tbd_idx; /* next transmit BD to clean */
87 u16 clean_tbd_num; /* the number of available transmit BDs */
92 /* Bit definitions and macros for IEVENT */
93 #define FEC_EIR_TXERR (0x00040000)
94 #define FEC_EIR_RXERR (0x00020000)
95 #undef FEC_EIR_CLEAR_ALL
96 #define FEC_EIR_CLEAR_ALL (0xFFFE0000)
98 /* Bit definitions and macros for R_HASH */
99 #define FEC_RHASH_FCE_DC (0x80000000)
100 #define FEC_RHASH_MULTCAST (0x40000000)
101 #define FEC_RHASH_HASH(x) (((x)&0x0000003F)<<24)
103 /* Bit definitions and macros for FEC_TFWR */
104 #undef FEC_TFWR_X_WMRK
105 #undef FEC_TFWR_X_WMRK_64
106 #undef FEC_TFWR_X_WMRK_128
107 #undef FEC_TFWR_X_WMRK_192
109 #define FEC_TFWR_X_WMRK(x) ((x)&0x0F)
110 #define FEC_TFWR_X_WMRK_64 (0x00)
111 #define FEC_TFWR_X_WMRK_128 (0x01)
112 #define FEC_TFWR_X_WMRK_192 (0x02)
113 #define FEC_TFWR_X_WMRK_256 (0x03)
114 #define FEC_TFWR_X_WMRK_320 (0x04)
115 #define FEC_TFWR_X_WMRK_384 (0x05)
116 #define FEC_TFWR_X_WMRK_448 (0x06)
117 #define FEC_TFWR_X_WMRK_512 (0x07)
118 #define FEC_TFWR_X_WMRK_576 (0x08)
119 #define FEC_TFWR_X_WMRK_640 (0x09)
120 #define FEC_TFWR_X_WMRK_704 (0x0A)
121 #define FEC_TFWR_X_WMRK_768 (0x0B)
122 #define FEC_TFWR_X_WMRK_832 (0x0C)
123 #define FEC_TFWR_X_WMRK_896 (0x0D)
124 #define FEC_TFWR_X_WMRK_960 (0x0E)
125 #define FEC_TFWR_X_WMRK_1024 (0x0F)
127 /* FIFO definitions */
128 /* Bit definitions and macros for FSTAT */
129 #define FIFO_STAT_IP (0x80000000)
130 #define FIFO_STAT_FRAME(x) (((x)&0x0000000F)<<24)
131 #define FIFO_STAT_FAE (0x00800000)
132 #define FIFO_STAT_RXW (0x00400000)
133 #define FIFO_STAT_UF (0x00200000)
134 #define FIFO_STAT_OF (0x00100000)
135 #define FIFO_STAT_FR (0x00080000)
136 #define FIFO_STAT_FULL (0x00040000)
137 #define FIFO_STAT_ALARM (0x00020000)
138 #define FIFO_STAT_EMPTY (0x00010000)
140 /* Bit definitions and macros for FCTRL */
141 #define FIFO_CTRL_WCTL (0x40000000)
142 #define FIFO_CTRL_WFR (0x20000000)
143 #define FIFO_CTRL_FRAME (0x08000000)
144 #define FIFO_CTRL_GR(x) (((x)&0x00000007)<<24)
145 #define FIFO_CTRL_IPMASK (0x00800000)
146 #define FIFO_CTRL_FAEMASK (0x00400000)
147 #define FIFO_CTRL_RXWMASK (0x00200000)
148 #define FIFO_CTRL_UFMASK (0x00100000)
149 #define FIFO_CTRL_OFMASK (0x00080000)
151 #endif /* fsl_mcdmafec_h */