1 // SPDX-License-Identifier: GPL-2.0+
4 * (C) Copyright 2000-2003
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
13 #include <asm/immap.h>
16 #if defined(CONFIG_CMD_NET)
19 #include <asm/fsl_mcdmafec.h>
23 * Breath some life into the CPU...
25 * Set up the memory map,
26 * initialize a bunch of registers,
27 * initialize the UPM's
31 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
32 fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
33 xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB;
35 out_be32(&xlbarb->adrto, 0x2000);
36 out_be32(&xlbarb->datto, 0x2500);
37 out_be32(&xlbarb->busto, 0x3000);
39 out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT);
41 /* Master Priority Enable */
42 out_be32(&xlbarb->prien, 0xff);
43 out_be32(&xlbarb->pri, 0);
45 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
46 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
47 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
48 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
51 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
52 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
53 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
54 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
57 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
58 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
59 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
60 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
63 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
64 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
65 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
66 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
69 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
70 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
71 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
72 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
75 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
76 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
77 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
78 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
81 #ifdef CONFIG_SYS_I2C_FSL
82 out_be16(&gpio->par_feci2cirq,
83 GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA);
90 * initialize higher level parts of CPU like timers
94 #if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC)
95 MCD_initDma((dmaRegs *) (MMAP_MCDMA), (void *)(MMAP_SRAM + 512),
101 void uart_port_conf(int port)
103 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
104 u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
109 out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
112 out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1);
115 out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2);
118 out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3);
122 clrbits_8(pscsicr, 0x07);
125 #if defined(CONFIG_CMD_NET)
126 int fecpin_setclear(struct eth_device *dev, int setclear)
128 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
129 struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
132 if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
133 setbits_be16(&gpio->par_feci2cirq, 0xf000);
135 setbits_be16(&gpio->par_feci2cirq, 0x0fc0);
137 if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
138 clrbits_be16(&gpio->par_feci2cirq, 0xf000);
140 clrbits_be16(&gpio->par_feci2cirq, 0x0fc0);