1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 #include <asm/processor.h>
11 #include <asm/immap.h>
14 DECLARE_GLOBAL_DATA_PTR;
17 * Low Power Divider specifications
19 #define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
20 #define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
22 #define CLOCK_PLL_FVCO_MAX 540000000
23 #define CLOCK_PLL_FVCO_MIN 300000000
25 #define CLOCK_PLL_FSYS_MAX 266666666
26 #define CLOCK_PLL_FSYS_MIN 100000000
29 void clock_enter_limp(int lpdiv)
31 ccm_t *ccm = (ccm_t *)MMAP_CCM;
34 /* Check bounds of divider */
35 if (lpdiv < CLOCK_LPD_MIN)
36 lpdiv = CLOCK_LPD_MIN;
37 if (lpdiv > CLOCK_LPD_MAX)
38 lpdiv = CLOCK_LPD_MAX;
40 /* Round divider down to nearest power of two */
41 for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
43 #ifdef CONFIG_MCF5445x
44 /* Apply the divider to the system clock */
45 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
48 /* Enable Limp Mode */
49 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
53 * brief Exit Limp mode
54 * warning The PLL should be set and locked prior to exiting Limp mode
56 void clock_exit_limp(void)
58 ccm_t *ccm = (ccm_t *)MMAP_CCM;
59 pll_t *pll = (pll_t *)MMAP_PLL;
62 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
64 /* Wait for the PLL to lock */
65 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
69 #ifdef CONFIG_MCF5441x
70 void setup_5441x_clocks(void)
72 ccm_t *ccm = (ccm_t *)MMAP_CCM;
73 pll_t *pll = (pll_t *)MMAP_PLL;
74 int temp, vco = 0, bootmod_ccr, pdr;
76 bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14;
78 switch (bootmod_ccr) {
80 out_be32(&pll->pcr, 0x00000013);
81 out_be32(&pll->pdr, 0x00e70c61);
90 /*Change frequency for Modelo SER1 USB host*/
91 #ifdef CONFIG_LOW_MCFCLK
92 temp = in_be32(&pll->pcr);
95 out_be32(&pll->pcr, temp);
97 temp = in_be32(&pll->pdr);
100 out_be32(&pll->pdr, temp);
104 setbits_be16(&ccm->misccr2, 0x02);
106 vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) *
107 CONFIG_SYS_INPUT_CLKSRC;
108 gd->arch.vco_clk = vco;
110 gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
112 pdr = in_be32(&pll->pdr);
113 temp = (pdr & PLL_DR_OUTDIV1_BITS) + 1;
114 gd->cpu_clk = vco / temp; /* cpu clock */
115 gd->arch.flb_clk = vco / temp; /* FlexBus clock */
116 gd->arch.flb_clk >>= 1;
117 if (in_be16(&ccm->misccr2) & 2) /* fsys/4 */
118 gd->arch.flb_clk >>= 1;
120 temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
121 gd->bus_clk = vco / temp; /* bus clock */
123 temp = ((pdr & PLL_DR_OUTDIV3_BITS) >> 10) + 1;
124 gd->arch.sdhc_clk = vco / temp;
128 #ifdef CONFIG_MCF5445x
129 void setup_5445x_clocks(void)
131 ccm_t *ccm = (ccm_t *)MMAP_CCM;
132 pll_t *pll = (pll_t *)MMAP_PLL;
133 int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
134 int pllmult_pci[] = { 12, 6, 16, 8 };
135 int vco = 0, temp, fbtemp, pcrvalue;
136 int *pPllmult = NULL;
142 #ifdef CONFIG_M54455EVB
143 u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
147 /* To determine PCI is present or not */
148 if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
149 ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
150 pPllmult = &pllmult_pci[0];
151 fbpll_mask = 3; /* 11b */
156 pPllmult = &pllmult_nopci[0];
157 fbpll_mask = 7; /* 111b */
164 #ifdef CONFIG_M54455EVB
165 bootmode = (in_8(cpld) & 0x03);
168 /* Temporary read from CCR- fixed fb issue, must be the same clock
169 as pci or input clock, causing cpld/fpga read inconsistancy */
170 fbtemp = pPllmult[ccm->ccr & fbpll_mask];
172 /* Break down into small pieces, code still in flex bus */
173 pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF;
175 pcrvalue |= PLL_PCR_OUTDIV3(temp);
177 out_be32(&pll->pcr, pcrvalue);
180 #ifdef CONFIG_M54451EVB
181 /* No external logic to read the bootmode, hard coded from built */
187 /* default value is 16 mul, set to 20 mul */
188 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000;
189 out_be32(&pll->pcr, pcrvalue);
190 while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK)
197 vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC;
199 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
200 /* invaild range, re-set in PCR */
201 int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
204 j = (in_be32(&pll->pcr) & 0xFF000000) >> 24;
205 for (i = j; i < 0xFF; i++) {
206 vco = i * CONFIG_SYS_INPUT_CLKSRC;
207 if (vco >= CLOCK_PLL_FVCO_MIN) {
209 if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
215 pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF;
216 fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
217 pcrvalue |= ((i << 24) | fbtemp);
219 out_be32(&pll->pcr, pcrvalue);
221 gd->arch.vco_clk = vco; /* Vco clock */
222 } else if (bootmode == 2) {
224 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
225 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
227 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
228 pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24;
229 out_be32(&pll->pcr, pcrvalue);
230 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
232 gd->arch.vco_clk = vco; /* Vco clock */
233 } else if (bootmode == 3) {
235 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
236 gd->arch.vco_clk = vco; /* Vco clock */
239 if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
242 gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
244 temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
245 gd->cpu_clk = vco / temp; /* cpu clock */
247 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
248 gd->bus_clk = vco / temp; /* bus clock */
250 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
251 gd->arch.flb_clk = vco / temp; /* FlexBus clock */
255 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
256 gd->pci_clk = vco / temp; /* PCI clock */
261 #ifdef CONFIG_SYS_I2C_FSL
262 gd->arch.i2c1_clk = gd->bus_clk;
267 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
270 #ifdef CONFIG_MCF5441x
271 setup_5441x_clocks();
273 #ifdef CONFIG_MCF5445x
274 setup_5445x_clocks();
277 #ifdef CONFIG_SYS_FSL_I2C
278 gd->arch.i2c1_clk = gd->bus_clk;