3 * Josef Baumgartner <josef.baumgartner@telex.de>
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
9 * Arcturus Networks Inc. <www.arcturusnetworks.com>
11 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
12 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
13 * Hayden Fraser (Hayden.Fraser@freescale.com)
16 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
18 * SPDX-License-Identifier: GPL-2.0+
23 #include <asm/immap.h>
26 #if defined(CONFIG_CMD_NET)
33 /* Only 5272 Flexbus chipselect is different from the rest */
36 fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
38 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
39 && defined(CONFIG_SYS_CS0_CTRL))
40 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
41 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
42 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
44 #warning "Chip Select 0 are not initialized/used"
46 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
47 && defined(CONFIG_SYS_CS1_CTRL))
48 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
49 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
50 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
52 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
53 && defined(CONFIG_SYS_CS2_CTRL))
54 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
55 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
56 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
58 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
59 && defined(CONFIG_SYS_CS3_CTRL))
60 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
61 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
62 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
64 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
65 && defined(CONFIG_SYS_CS4_CTRL))
66 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
67 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
68 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
70 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
71 && defined(CONFIG_SYS_CS5_CTRL))
72 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
73 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
74 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
76 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
77 && defined(CONFIG_SYS_CS6_CTRL))
78 out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
79 out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
80 out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
82 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
83 && defined(CONFIG_SYS_CS7_CTRL))
84 out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
85 out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
86 out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
91 #if defined(CONFIG_M5208)
94 scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
96 #ifndef CONFIG_WATCHDOG
97 wdog_t *wdg = (wdog_t *) MMAP_WDOG;
99 /* Disable the watchdog if we aren't using it */
100 out_be16(&wdg->cr, 0);
103 out_be32(&scm1->mpr, 0x77777777);
104 out_be32(&scm1->pacra, 0);
105 out_be32(&scm1->pacrb, 0);
106 out_be32(&scm1->pacrc, 0);
107 out_be32(&scm1->pacrd, 0);
108 out_be32(&scm1->pacre, 0);
109 out_be32(&scm1->pacrf, 0);
111 /* FlexBus Chipselect */
117 /* initialize higher level parts of CPU like timers */
123 void uart_port_conf(int port)
125 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
130 clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
131 setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
134 clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
135 setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
138 #ifdef CONFIG_SYS_UART2_PRI_GPIO
139 clrbits_8(&gpio->par_timer,
140 ~(GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK));
141 setbits_8(&gpio->par_timer,
142 GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
144 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
145 clrbits_8(&gpio->par_feci2c,
146 ~(GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK));
147 setbits_8(&gpio->par_feci2c,
148 GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
150 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
151 clrbits_8(&gpio->par_feci2c,
152 ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK));
153 setbits_8(&gpio->par_feci2c,
154 GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
160 #if defined(CONFIG_CMD_NET)
161 int fecpin_setclear(struct eth_device *dev, int setclear)
163 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
166 setbits_8(&gpio->par_fec,
167 GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
168 setbits_8(&gpio->par_feci2c,
169 GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO);
171 clrbits_8(&gpio->par_fec,
172 ~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK));
173 clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK);
177 #endif /* CONFIG_CMD_NET */
178 #endif /* CONFIG_M5208 */
180 #if defined(CONFIG_M5253)
182 * Breath some life into the CPU...
184 * Set up the memory map,
185 * initialize a bunch of registers,
186 * initialize the UPM's
188 void cpu_init_f(void)
190 mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */
191 mbar_writeByte(MCFSIM_SYPCR, 0x00);
192 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
193 mbar_writeByte(MCFSIM_SWSR, 0x00);
194 mbar_writeByte(MCFSIM_SWDICR, 0x00);
195 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
196 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
197 mbar_writeByte(MCFSIM_I2CICR, 0x00);
198 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
199 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
200 mbar_writeByte(MCFSIM_ICR6, 0x00);
201 mbar_writeByte(MCFSIM_ICR7, 0x00);
202 mbar_writeByte(MCFSIM_ICR8, 0x00);
203 mbar_writeByte(MCFSIM_ICR9, 0x00);
204 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
206 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
207 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
208 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
210 /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
212 /* FlexBus Chipselect */
215 #ifdef CONFIG_SYS_I2C_FSL
216 CONFIG_SYS_I2C_PINMUX_REG =
217 CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
218 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
219 #ifdef CONFIG_SYS_I2C2_OFFSET
220 CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
221 CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
225 /* enable instruction cache now */
229 /*initialize higher level parts of CPU like timers */
235 void uart_port_conf(int port)
237 u32 *par = (u32 *) MMAP_PAR;
242 clrbits_be32(par, 0x00180000);
243 setbits_be32(par, 0x00180000);
246 clrbits_be32(par, 0x00000003);
247 clrbits_be32(par, 0xFFFFFFFC);
251 #endif /* #if defined(CONFIG_M5253) */
253 #if defined(CONFIG_M5271)
254 void cpu_init_f(void)
256 #ifndef CONFIG_WATCHDOG
257 /* Disable the watchdog if we aren't using it */
258 mbar_writeShort(MCF_WTM_WCR, 0);
261 /* FlexBus Chipselect */
264 #ifdef CONFIG_SYS_MCF_SYNCR
265 /* Set clockspeed according to board header file */
266 mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
268 /* Set clockspeed to 100MHz */
269 mbar_writeLong(MCF_FMPLL_SYNCR,
270 MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
272 while (!(mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK)) ;
276 * initialize higher level parts of CPU like timers
283 void uart_port_conf(int port)
290 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3;
291 temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD);
292 mbar_writeShort(MCF_GPIO_PAR_UART, temp);
295 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF;
296 temp |= (MCF_GPIO_PAR_UART_U1RXD_UART1 | MCF_GPIO_PAR_UART_U1TXD_UART1);
297 mbar_writeShort(MCF_GPIO_PAR_UART, temp);
300 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF;
302 mbar_writeShort(MCF_GPIO_PAR_UART, temp);
307 #if defined(CONFIG_CMD_NET)
308 int fecpin_setclear(struct eth_device *dev, int setclear)
311 /* Enable Ethernet pins */
312 mbar_writeByte(MCF_GPIO_PAR_FECI2C,
313 (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));
319 #endif /* CONFIG_CMD_NET */
321 #if defined(CONFIG_CF_QSPI)
323 /* Configure PIOs for SIN, SOUT, and SCK */
324 void cfspi_port_conf(void)
326 mbar_writeByte(MCF_GPIO_PAR_QSPI,
327 MCF_GPIO_PAR_QSPI_SIN_SIN |
328 MCF_GPIO_PAR_QSPI_SOUT_SOUT |
329 MCF_GPIO_PAR_QSPI_SCK_SCK);
331 #endif /* CONFIG_CF_QSPI */
333 #endif /* CONFIG_M5271 */
335 #if defined(CONFIG_M5272)
337 * Breath some life into the CPU...
339 * Set up the memory map,
340 * initialize a bunch of registers,
341 * initialize the UPM's
343 void cpu_init_f(void)
345 /* if we come from RAM we assume the CPU is
346 * already initialized.
348 #ifndef CONFIG_MONITOR_IS_IN_RAM
349 sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
350 gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
351 csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
353 out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
354 out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
357 out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
358 out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
359 out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
360 out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
361 out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
362 out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
363 out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
365 /* Memory Controller: */
366 out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
367 out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM);
369 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
370 out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM);
371 out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM);
374 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
375 out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM);
376 out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM);
379 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
380 out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM);
381 out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM);
384 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
385 out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM);
386 out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM);
389 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
390 out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM);
391 out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM);
394 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
395 out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM);
396 out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM);
399 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
400 out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM);
401 out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM);
404 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
406 /* enable instruction cache now */
412 * initialize higher level parts of CPU like timers
419 void uart_port_conf(int port)
421 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
426 clrbits_be32(&gpio->gpio_pbcnt,
427 GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
428 setbits_be32(&gpio->gpio_pbcnt,
429 GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
432 clrbits_be32(&gpio->gpio_pdcnt,
433 GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
434 setbits_be32(&gpio->gpio_pdcnt,
435 GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
440 #if defined(CONFIG_CMD_NET)
441 int fecpin_setclear(struct eth_device *dev, int setclear)
443 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
446 setbits_be32(&gpio->gpio_pbcnt,
447 GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
448 GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
449 GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
450 GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3);
455 #endif /* CONFIG_CMD_NET */
456 #endif /* #if defined(CONFIG_M5272) */
458 #if defined(CONFIG_M5275)
461 * Breathe some life into the CPU...
463 * Set up the memory map,
464 * initialize a bunch of registers,
465 * initialize the UPM's
467 void cpu_init_f(void)
470 * if we come from RAM we assume the CPU is
471 * already initialized.
474 #ifndef CONFIG_MONITOR_IS_IN_RAM
475 wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
476 gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
478 /* Kill watchdog so we can initialize the PLL */
479 out_be16(&wdog_reg->wcr, 0);
481 /* FlexBus Chipselect */
483 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
485 #ifdef CONFIG_SYS_I2C_FSL
486 CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
487 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
490 /* enable instruction cache now */
495 * initialize higher level parts of CPU like timers
502 void uart_port_conf(int port)
504 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
509 clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
510 setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
513 clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
514 setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
517 clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
518 setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
523 #if defined(CONFIG_CMD_NET)
524 int fecpin_setclear(struct eth_device *dev, int setclear)
526 struct fec_info_s *info = (struct fec_info_s *) dev->priv;
527 gpio_t *gpio = (gpio_t *)MMAP_GPIO;
530 /* Enable Ethernet pins */
531 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
532 setbits_be16(&gpio->par_feci2c, 0x0f00);
533 setbits_8(&gpio->par_fec0hl, 0xc0);
535 setbits_be16(&gpio->par_feci2c, 0x00a0);
536 setbits_8(&gpio->par_fec1hl, 0xc0);
539 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
540 clrbits_be16(&gpio->par_feci2c, 0x0f00);
541 clrbits_8(&gpio->par_fec0hl, 0xc0);
543 clrbits_be16(&gpio->par_feci2c, 0x00a0);
544 clrbits_8(&gpio->par_fec1hl, 0xc0);
550 #endif /* CONFIG_CMD_NET */
551 #endif /* #if defined(CONFIG_M5275) */
553 #if defined(CONFIG_M5282)
555 * Breath some life into the CPU...
557 * Set up the memory map,
558 * initialize a bunch of registers,
559 * initialize the UPM's
561 void cpu_init_f(void)
563 #ifndef CONFIG_WATCHDOG
564 /* disable watchdog if we aren't using it */
568 #ifndef CONFIG_MONITOR_IS_IN_RAM
571 MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
572 MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
573 while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
575 MCFGPIO_PBCDPAR = 0xc0;
577 /* Set up the GPIO ports */
578 #ifdef CONFIG_SYS_PEPAR
579 MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
581 #ifdef CONFIG_SYS_PFPAR
582 MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
584 #ifdef CONFIG_SYS_PJPAR
585 MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
587 #ifdef CONFIG_SYS_PSDPAR
588 MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
590 #ifdef CONFIG_SYS_PASPAR
591 MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
593 #ifdef CONFIG_SYS_PEHLPAR
594 MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
596 #ifdef CONFIG_SYS_PQSPAR
597 MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
599 #ifdef CONFIG_SYS_PTCPAR
600 MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
602 #if defined(CONFIG_SYS_PORTTC)
603 MCFGPIO_PORTTC = CONFIG_SYS_PORTTC;
605 #if defined(CONFIG_SYS_DDRTC)
606 MCFGPIO_DDRTC = CONFIG_SYS_DDRTC;
608 #ifdef CONFIG_SYS_PTDPAR
609 MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
611 #ifdef CONFIG_SYS_PUAPAR
612 MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
615 #if defined(CONFIG_SYS_DDRD)
616 MCFGPIO_DDRD = CONFIG_SYS_DDRD;
618 #ifdef CONFIG_SYS_DDRUA
619 MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
622 /* FlexBus Chipselect */
625 #endif /* CONFIG_MONITOR_IS_IN_RAM */
627 /* defer enabling cache until boot (see do_go) */
628 /* icache_enable(); */
632 * initialize higher level parts of CPU like timers
639 void uart_port_conf(int port)
644 MCFGPIO_PUAPAR &= 0xFc;
645 MCFGPIO_PUAPAR |= 0x03;
648 MCFGPIO_PUAPAR &= 0xF3;
649 MCFGPIO_PUAPAR |= 0x0C;
652 MCFGPIO_PASPAR &= 0xFF0F;
653 MCFGPIO_PASPAR |= 0x00A0;
658 #if defined(CONFIG_CMD_NET)
659 int fecpin_setclear(struct eth_device *dev, int setclear)
662 MCFGPIO_PASPAR |= 0x0F00;
663 MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
665 MCFGPIO_PASPAR &= 0xF0FF;
666 MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
670 #endif /* CONFIG_CMD_NET */
673 #if defined(CONFIG_M5249)
675 * Breath some life into the CPU...
677 * Set up the memory map,
678 * initialize a bunch of registers,
679 * initialize the UPM's
681 void cpu_init_f(void)
684 * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
685 * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
686 * which is their primary function.
689 mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
690 mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
691 mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
692 mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
693 mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
694 mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
698 * You can verify these values by using dBug's 'ird'
699 * (Internal Register Display) command
703 mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
704 mbar_writeByte(MCFSIM_SYPCR, 0x00);
705 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
706 mbar_writeByte(MCFSIM_SWSR, 0x00);
707 mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
708 mbar_writeByte(MCFSIM_SWDICR, 0x00);
709 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
710 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
711 mbar_writeByte(MCFSIM_I2CICR, 0x00);
712 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
713 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
714 mbar_writeByte(MCFSIM_ICR6, 0x00);
715 mbar_writeByte(MCFSIM_ICR7, 0x00);
716 mbar_writeByte(MCFSIM_ICR8, 0x00);
717 mbar_writeByte(MCFSIM_ICR9, 0x00);
718 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
720 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
721 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
722 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
723 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
725 /* Setup interrupt priorities for gpio7 */
726 /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
728 /* IDE Config registers */
729 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
730 mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
732 /* FlexBus Chipselect */
735 /* enable instruction cache now */
740 * initialize higher level parts of CPU like timers
747 void uart_port_conf(int port)
750 #endif /* #if defined(CONFIG_M5249) */