3 * Graeme Russ <graeme.russ@gmail.com>.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor-flags.h>
27 #include <asm/ic/sc520.h>
34 * How to enable Cache-As-RAM for the AMD Elan SC520:
35 * 1. Turn off the CPU Cache (may not be strictly required)
36 * 2. Set code execution PAR (usually the BOOTCS region) to be
38 * 3. Create a Cachable PAR Region for an area of memory which is
39 * a) NOT where the code is being executed
40 * b) NOT SDRAM (Controller not initialised yet)
41 * c) WILL response to read requests
42 * The easiest way to do this is to create a second BOOTCS
43 * PAR mappnig with an address != the PAR in step 2
44 * 4. Issue a wbinvd to invalidate the CPU cache
45 * 5. Turn on the CPU Cache
46 * 6. Read 16kB from the cached PAR region setup in step 3
47 * 7. Turn off the CPU Cache (but DO NOT issue a wbinvd)
49 * The following code uses PAR2 as the cached PAR (PAR0 and PAR1
50 * are avoided as these are the only two PARs which can be used
51 * as PCI BUS Memory regions which the board might require)
53 * The configuration of PAR2 must be set in the board configuration
54 * file as CONFIG_SYS_SC520_CAR_PAR
57 /* Configure Cache-As-RAM PAR */
58 movl $CONFIG_SYS_SC520_CAR_PAR, %eax
59 movl $SC520_PAR2, %edi
62 /* Trash the cache then turn it on */
65 andl $~(X86_CR0_NW | X86_CR0_CD), %eax
69 * The cache is now enabled and empty. Map a region of memory to
70 * it by reading that region.
72 movl $CONFIG_SYS_CAR_ADDR, %esi
73 movl $CONFIG_SYS_CAR_SIZE, %ecx
74 shrl $2, %ecx /* we are reading longs */
78 /* Turn off the cache, but don't trash it */
80 orl $(X86_CR0_NW | X86_CR0_CD), %eax
83 /* Clear the CAR region */
85 movl $CONFIG_SYS_CAR_ADDR, %edi
86 movl $CONFIG_SYS_CAR_SIZE, %ecx
87 shrl $2, %ecx /* we are writing longs */
91 * Done - We should now have CONFIG_SYS_CAR_SIZE bytes of