3 * Graeme Russ, graeme.russ@gmail.com.
6 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
8 * Portions of this file are derived from the Linux kernel source
9 * Copyright (C) 1991, 1992 Linus Torvalds
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/interrupt.h>
33 #define DECLARE_INTERRUPT(x) \
35 ".hidden irq_"#x"\n" \
36 ".type irq_"#x", @function\n" \
39 "jmp irq_common_entry\n"
42 * Volatile isn't enough to prevent the compiler from reordering the
43 * read/write functions for the control registers and messing everything up.
44 * A memory clobber would solve the problem, but would prevent reordering of
45 * all loads stores around it, which can hurt performance. Solution is to
46 * use a variable and mimic reads and writes to it to enforce serialization
48 static unsigned long __force_order;
50 static inline unsigned long read_cr0(void)
53 asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
57 static inline unsigned long read_cr2(void)
60 asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
64 static inline unsigned long read_cr3(void)
67 asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
71 static inline unsigned long read_cr4(void)
74 asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
78 static inline unsigned long get_debugreg(int regno)
80 unsigned long val = 0; /* Damn you, gcc! */
84 asm("mov %%db0, %0" :"=r" (val));
87 asm("mov %%db1, %0" :"=r" (val));
90 asm("mov %%db2, %0" :"=r" (val));
93 asm("mov %%db3, %0" :"=r" (val));
96 asm("mov %%db6, %0" :"=r" (val));
99 asm("mov %%db7, %0" :"=r" (val));
107 void dump_regs(struct pt_regs *regs)
109 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
110 unsigned long d0, d1, d2, d3, d6, d7;
112 printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
113 (u16)regs->xcs, regs->eip, regs->eflags);
115 printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
116 regs->eax, regs->ebx, regs->ecx, regs->edx);
117 printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
118 regs->esi, regs->edi, regs->ebp, regs->esp);
119 printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
120 (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs, (u16)regs->xgs, (u16)regs->xss);
127 printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
130 d0 = get_debugreg(0);
131 d1 = get_debugreg(1);
132 d2 = get_debugreg(2);
133 d3 = get_debugreg(3);
135 printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
138 d6 = get_debugreg(6);
139 d7 = get_debugreg(7);
140 printf("DR6: %08lx DR7: %08lx\n",
150 } __attribute__ ((packed));
154 unsigned long address;
155 unsigned short segment;
156 } __attribute__((packed));
158 struct idt_entry idt[256];
160 struct desc_ptr idt_ptr;
162 static inline void load_idt(const struct desc_ptr *dtr)
164 asm volatile("cs lidt %0"::"m" (*dtr));
167 void set_vector(u8 intnum, void *routine)
169 idt[intnum].base_high = (u16)((u32)(routine) >> 16);
170 idt[intnum].base_low = (u16)((u32)(routine) & 0xffff);
176 int cpu_init_interrupts(void)
180 int irq_entry_size = irq_1 - irq_0;
181 void *irq_entry = (void *)irq_0;
183 /* Just in case... */
184 disable_interrupts();
187 for (i=0;i<256;i++) {
188 idt[i].access = 0x8e;
190 idt[i].selector = 0x10;
191 set_vector(i, irq_entry);
192 irq_entry += irq_entry_size;
195 idt_ptr.size = 256 * 8;
196 idt_ptr.address = (unsigned long) idt;
197 idt_ptr.segment = 0x18;
201 /* It is now safe to enable interrupts */
207 void __do_irq(int irq)
209 printf("Unhandled IRQ : %d\n", irq);
211 void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
213 void enable_interrupts(void)
218 int disable_interrupts(void)
222 asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
224 return (flags&0x200); /* IE flags is bit 9 */
227 /* IRQ Low-Level Service Routine */
228 __isr__ irq_llsr(struct pt_regs *regs)
231 * For detailed description of each exception, refer to:
232 * Intel® 64 and IA-32 Architectures Software Developer's Manual
233 * Volume 1: Basic Architecture
234 * Order Number: 253665-029US, November 2008
235 * Table 6-1. Exceptions and Interrupts
237 switch (regs->orig_eax) {
239 printf("Divide Error (Division by zero)\n");
244 printf("Debug Interrupt (Single step)\n");
248 printf("NMI Interrupt\n");
252 printf("Breakpoint\n");
256 printf("Overflow\n");
261 printf("BOUND Range Exceeded\n");
266 printf("Invalid Opcode (UnDefined Opcode)\n");
271 printf("Device Not Available (No Math Coprocessor)\n");
276 printf("Double fault\n");
281 printf("Co-processor segment overrun\n");
286 printf("Invalid TSS\n");
290 printf("Segment Not Present\n");
295 printf("Stack Segment Fault\n");
300 printf("General Protection\n");
304 printf("Page fault\n");
309 printf("Floating-Point Error (Math Fault)\n");
313 printf("Alignment check\n");
317 printf("Machine Check\n");
321 printf("SIMD Floating-Point Exception\n");
337 printf("Reserved Exception\n");
342 /* Hardware or User IRQ */
343 do_irq(regs->orig_eax);
348 * OK - This looks really horrible, but it serves a purpose - It helps create
349 * fully relocatable code.
350 * - The call to irq_llsr will be a relative jump
351 * - The IRQ entries will be guaranteed to be in order
352 * Interrupt entries are now very small (a push and a jump) but they are
353 * now slower (all registers pushed on stack which provides complete
354 * crash dumps in the low level handlers
356 asm(".globl irq_common_entry\n" \
357 ".hidden irq_common_entry\n" \
358 ".type irq_common_entry, @function\n" \
359 "irq_common_entry:\n" \
392 DECLARE_INTERRUPT(0) \
393 DECLARE_INTERRUPT(1) \
394 DECLARE_INTERRUPT(2) \
395 DECLARE_INTERRUPT(3) \
396 DECLARE_INTERRUPT(4) \
397 DECLARE_INTERRUPT(5) \
398 DECLARE_INTERRUPT(6) \
399 DECLARE_INTERRUPT(7) \
400 DECLARE_INTERRUPT(8) \
401 DECLARE_INTERRUPT(9) \
402 DECLARE_INTERRUPT(10) \
403 DECLARE_INTERRUPT(11) \
404 DECLARE_INTERRUPT(12) \
405 DECLARE_INTERRUPT(13) \
406 DECLARE_INTERRUPT(14) \
407 DECLARE_INTERRUPT(15) \
408 DECLARE_INTERRUPT(16) \
409 DECLARE_INTERRUPT(17) \
410 DECLARE_INTERRUPT(18) \
411 DECLARE_INTERRUPT(19) \
412 DECLARE_INTERRUPT(20) \
413 DECLARE_INTERRUPT(21) \
414 DECLARE_INTERRUPT(22) \
415 DECLARE_INTERRUPT(23) \
416 DECLARE_INTERRUPT(24) \
417 DECLARE_INTERRUPT(25) \
418 DECLARE_INTERRUPT(26) \
419 DECLARE_INTERRUPT(27) \
420 DECLARE_INTERRUPT(28) \
421 DECLARE_INTERRUPT(29) \
422 DECLARE_INTERRUPT(30) \
423 DECLARE_INTERRUPT(31) \
424 DECLARE_INTERRUPT(32) \
425 DECLARE_INTERRUPT(33) \
426 DECLARE_INTERRUPT(34) \
427 DECLARE_INTERRUPT(35) \
428 DECLARE_INTERRUPT(36) \
429 DECLARE_INTERRUPT(37) \
430 DECLARE_INTERRUPT(38) \
431 DECLARE_INTERRUPT(39) \
432 DECLARE_INTERRUPT(40) \
433 DECLARE_INTERRUPT(41) \
434 DECLARE_INTERRUPT(42) \
435 DECLARE_INTERRUPT(43) \
436 DECLARE_INTERRUPT(44) \
437 DECLARE_INTERRUPT(45) \
438 DECLARE_INTERRUPT(46) \
439 DECLARE_INTERRUPT(47) \
440 DECLARE_INTERRUPT(48) \
441 DECLARE_INTERRUPT(49) \
442 DECLARE_INTERRUPT(50) \
443 DECLARE_INTERRUPT(51) \
444 DECLARE_INTERRUPT(52) \
445 DECLARE_INTERRUPT(53) \
446 DECLARE_INTERRUPT(54) \
447 DECLARE_INTERRUPT(55) \
448 DECLARE_INTERRUPT(56) \
449 DECLARE_INTERRUPT(57) \
450 DECLARE_INTERRUPT(58) \
451 DECLARE_INTERRUPT(59) \
452 DECLARE_INTERRUPT(60) \
453 DECLARE_INTERRUPT(61) \
454 DECLARE_INTERRUPT(62) \
455 DECLARE_INTERRUPT(63) \
456 DECLARE_INTERRUPT(64) \
457 DECLARE_INTERRUPT(65) \
458 DECLARE_INTERRUPT(66) \
459 DECLARE_INTERRUPT(67) \
460 DECLARE_INTERRUPT(68) \
461 DECLARE_INTERRUPT(69) \
462 DECLARE_INTERRUPT(70) \
463 DECLARE_INTERRUPT(71) \
464 DECLARE_INTERRUPT(72) \
465 DECLARE_INTERRUPT(73) \
466 DECLARE_INTERRUPT(74) \
467 DECLARE_INTERRUPT(75) \
468 DECLARE_INTERRUPT(76) \
469 DECLARE_INTERRUPT(77) \
470 DECLARE_INTERRUPT(78) \
471 DECLARE_INTERRUPT(79) \
472 DECLARE_INTERRUPT(80) \
473 DECLARE_INTERRUPT(81) \
474 DECLARE_INTERRUPT(82) \
475 DECLARE_INTERRUPT(83) \
476 DECLARE_INTERRUPT(84) \
477 DECLARE_INTERRUPT(85) \
478 DECLARE_INTERRUPT(86) \
479 DECLARE_INTERRUPT(87) \
480 DECLARE_INTERRUPT(88) \
481 DECLARE_INTERRUPT(89) \
482 DECLARE_INTERRUPT(90) \
483 DECLARE_INTERRUPT(91) \
484 DECLARE_INTERRUPT(92) \
485 DECLARE_INTERRUPT(93) \
486 DECLARE_INTERRUPT(94) \
487 DECLARE_INTERRUPT(95) \
488 DECLARE_INTERRUPT(97) \
489 DECLARE_INTERRUPT(96) \
490 DECLARE_INTERRUPT(98) \
491 DECLARE_INTERRUPT(99) \
492 DECLARE_INTERRUPT(100) \
493 DECLARE_INTERRUPT(101) \
494 DECLARE_INTERRUPT(102) \
495 DECLARE_INTERRUPT(103) \
496 DECLARE_INTERRUPT(104) \
497 DECLARE_INTERRUPT(105) \
498 DECLARE_INTERRUPT(106) \
499 DECLARE_INTERRUPT(107) \
500 DECLARE_INTERRUPT(108) \
501 DECLARE_INTERRUPT(109) \
502 DECLARE_INTERRUPT(110) \
503 DECLARE_INTERRUPT(111) \
504 DECLARE_INTERRUPT(112) \
505 DECLARE_INTERRUPT(113) \
506 DECLARE_INTERRUPT(114) \
507 DECLARE_INTERRUPT(115) \
508 DECLARE_INTERRUPT(116) \
509 DECLARE_INTERRUPT(117) \
510 DECLARE_INTERRUPT(118) \
511 DECLARE_INTERRUPT(119) \
512 DECLARE_INTERRUPT(120) \
513 DECLARE_INTERRUPT(121) \
514 DECLARE_INTERRUPT(122) \
515 DECLARE_INTERRUPT(123) \
516 DECLARE_INTERRUPT(124) \
517 DECLARE_INTERRUPT(125) \
518 DECLARE_INTERRUPT(126) \
519 DECLARE_INTERRUPT(127) \
520 DECLARE_INTERRUPT(128) \
521 DECLARE_INTERRUPT(129) \
522 DECLARE_INTERRUPT(130) \
523 DECLARE_INTERRUPT(131) \
524 DECLARE_INTERRUPT(132) \
525 DECLARE_INTERRUPT(133) \
526 DECLARE_INTERRUPT(134) \
527 DECLARE_INTERRUPT(135) \
528 DECLARE_INTERRUPT(136) \
529 DECLARE_INTERRUPT(137) \
530 DECLARE_INTERRUPT(138) \
531 DECLARE_INTERRUPT(139) \
532 DECLARE_INTERRUPT(140) \
533 DECLARE_INTERRUPT(141) \
534 DECLARE_INTERRUPT(142) \
535 DECLARE_INTERRUPT(143) \
536 DECLARE_INTERRUPT(144) \
537 DECLARE_INTERRUPT(145) \
538 DECLARE_INTERRUPT(146) \
539 DECLARE_INTERRUPT(147) \
540 DECLARE_INTERRUPT(148) \
541 DECLARE_INTERRUPT(149) \
542 DECLARE_INTERRUPT(150) \
543 DECLARE_INTERRUPT(151) \
544 DECLARE_INTERRUPT(152) \
545 DECLARE_INTERRUPT(153) \
546 DECLARE_INTERRUPT(154) \
547 DECLARE_INTERRUPT(155) \
548 DECLARE_INTERRUPT(156) \
549 DECLARE_INTERRUPT(157) \
550 DECLARE_INTERRUPT(158) \
551 DECLARE_INTERRUPT(159) \
552 DECLARE_INTERRUPT(160) \
553 DECLARE_INTERRUPT(161) \
554 DECLARE_INTERRUPT(162) \
555 DECLARE_INTERRUPT(163) \
556 DECLARE_INTERRUPT(164) \
557 DECLARE_INTERRUPT(165) \
558 DECLARE_INTERRUPT(166) \
559 DECLARE_INTERRUPT(167) \
560 DECLARE_INTERRUPT(168) \
561 DECLARE_INTERRUPT(169) \
562 DECLARE_INTERRUPT(170) \
563 DECLARE_INTERRUPT(171) \
564 DECLARE_INTERRUPT(172) \
565 DECLARE_INTERRUPT(173) \
566 DECLARE_INTERRUPT(174) \
567 DECLARE_INTERRUPT(175) \
568 DECLARE_INTERRUPT(176) \
569 DECLARE_INTERRUPT(177) \
570 DECLARE_INTERRUPT(178) \
571 DECLARE_INTERRUPT(179) \
572 DECLARE_INTERRUPT(180) \
573 DECLARE_INTERRUPT(181) \
574 DECLARE_INTERRUPT(182) \
575 DECLARE_INTERRUPT(183) \
576 DECLARE_INTERRUPT(184) \
577 DECLARE_INTERRUPT(185) \
578 DECLARE_INTERRUPT(186) \
579 DECLARE_INTERRUPT(187) \
580 DECLARE_INTERRUPT(188) \
581 DECLARE_INTERRUPT(189) \
582 DECLARE_INTERRUPT(190) \
583 DECLARE_INTERRUPT(191) \
584 DECLARE_INTERRUPT(192) \
585 DECLARE_INTERRUPT(193) \
586 DECLARE_INTERRUPT(194) \
587 DECLARE_INTERRUPT(195) \
588 DECLARE_INTERRUPT(196) \
589 DECLARE_INTERRUPT(197) \
590 DECLARE_INTERRUPT(198) \
591 DECLARE_INTERRUPT(199) \
592 DECLARE_INTERRUPT(200) \
593 DECLARE_INTERRUPT(201) \
594 DECLARE_INTERRUPT(202) \
595 DECLARE_INTERRUPT(203) \
596 DECLARE_INTERRUPT(204) \
597 DECLARE_INTERRUPT(205) \
598 DECLARE_INTERRUPT(206) \
599 DECLARE_INTERRUPT(207) \
600 DECLARE_INTERRUPT(208) \
601 DECLARE_INTERRUPT(209) \
602 DECLARE_INTERRUPT(210) \
603 DECLARE_INTERRUPT(211) \
604 DECLARE_INTERRUPT(212) \
605 DECLARE_INTERRUPT(213) \
606 DECLARE_INTERRUPT(214) \
607 DECLARE_INTERRUPT(215) \
608 DECLARE_INTERRUPT(216) \
609 DECLARE_INTERRUPT(217) \
610 DECLARE_INTERRUPT(218) \
611 DECLARE_INTERRUPT(219) \
612 DECLARE_INTERRUPT(220) \
613 DECLARE_INTERRUPT(221) \
614 DECLARE_INTERRUPT(222) \
615 DECLARE_INTERRUPT(223) \
616 DECLARE_INTERRUPT(224) \
617 DECLARE_INTERRUPT(225) \
618 DECLARE_INTERRUPT(226) \
619 DECLARE_INTERRUPT(227) \
620 DECLARE_INTERRUPT(228) \
621 DECLARE_INTERRUPT(229) \
622 DECLARE_INTERRUPT(230) \
623 DECLARE_INTERRUPT(231) \
624 DECLARE_INTERRUPT(232) \
625 DECLARE_INTERRUPT(233) \
626 DECLARE_INTERRUPT(234) \
627 DECLARE_INTERRUPT(235) \
628 DECLARE_INTERRUPT(236) \
629 DECLARE_INTERRUPT(237) \
630 DECLARE_INTERRUPT(238) \
631 DECLARE_INTERRUPT(239) \
632 DECLARE_INTERRUPT(240) \
633 DECLARE_INTERRUPT(241) \
634 DECLARE_INTERRUPT(242) \
635 DECLARE_INTERRUPT(243) \
636 DECLARE_INTERRUPT(244) \
637 DECLARE_INTERRUPT(245) \
638 DECLARE_INTERRUPT(246) \
639 DECLARE_INTERRUPT(247) \
640 DECLARE_INTERRUPT(248) \
641 DECLARE_INTERRUPT(249) \
642 DECLARE_INTERRUPT(250) \
643 DECLARE_INTERRUPT(251) \
644 DECLARE_INTERRUPT(252) \
645 DECLARE_INTERRUPT(253) \
646 DECLARE_INTERRUPT(254) \
647 DECLARE_INTERRUPT(255));