arch/blackfin/lib/outs.S

   1 /*
   2  * Implementation of outs{bwl} for BlackFin processors using zero overhead loops.
   3  *
   4  * Copyright 2005-2009 Analog Devices Inc.
   5  *                2005 BuyWays BV
   6  *                      Bas Vermeulen <bas@buyways.nl>
   7  *
   8  * Licensed under the GPL-2.
   9  */
  10
  11 #include <asm/linkage.h>
  12
  13 .align 2
  14
  15 ENTRY(_outsl)
  16         P0 = R0;        /* P0 = port */
  17         P1 = R1;        /* P1 = address */
  18         P2 = R2;        /* P2 = count */
  19
  20         LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
  21 .Llong_loop_s: R0 = [P1++];
  22 .Llong_loop_e: [P0] = R0;
  23         RTS;
  24 ENDPROC(_outsl)
  25
  26 ENTRY(_outsw)
  27         P0 = R0;        /* P0 = port */
  28         P1 = R1;        /* P1 = address */
  29         P2 = R2;        /* P2 = count */
  30
  31         LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
  32 .Lword_loop_s: R0 = W[P1++];
  33 .Lword_loop_e: W[P0] = R0;
  34         RTS;
  35 ENDPROC(_outsw)
  36
  37 ENTRY(_outsb)
  38         P0 = R0;        /* P0 = port */
  39         P1 = R1;        /* P1 = address */
  40         P2 = R2;        /* P2 = count */
  41
  42         LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
  43 .Lbyte_loop_s: R0 = B[P1++];
  44 .Lbyte_loop_e: B[P0] = R0;
  45         RTS;
  46 ENDPROC(_outsb)
  47
  48 ENTRY(_outsw_8)
  49         P0 = R0;        /* P0 = port */
  50         P1 = R1;        /* P1 = address */
  51         P2 = R2;        /* P2 = count */
  52
  53         LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
  54 .Lword8_loop_s: R1 = B[P1++];
  55                 R0 = B[P1++];
  56                 R0 = R0 << 8;
  57                 R0 = R0 + R1;
  58 .Lword8_loop_e: W[P0] = R0;
  59         RTS;
  60 ENDPROC(_outsw_8)