1 /* DO NOT EDIT THIS FILE
2 * Automatically generated by generate-def-headers.xsl
3 * DO NOT EDIT THIS FILE
6 #ifndef __BFIN_DEF_ADSP_BF526_proc__
7 #define __BFIN_DEF_ADSP_BF526_proc__
9 #include "../mach-common/ADSP-EDN-core_def.h"
11 #include "ADSP-EDN-BF52x-extended_def.h"
13 #define PLL_CTL 0xFFC00000 /* PLL Control Register */
14 #define PLL_DIV 0xFFC00004 /* PLL Divide Register */
15 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
16 #define PLL_STAT 0xFFC0000C /* PLL Status Register */
17 #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
18 #define CHIPID 0xFFC00014
19 #define SWRST 0xFFC00100 /* Software Reset Register */
20 #define SYSCR 0xFFC00104 /* System Configuration register */
21 #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
22 #define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
23 #define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
24 #define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
25 #define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
26 #define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
27 #define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
28 #define EMAC_FLC 0xFFC0301C /* Flow Control Register */
29 #define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
30 #define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
31 #define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
32 #define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
33 #define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
34 #define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
35 #define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
36 #define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
37 #define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
38 #define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
39 #define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
40 #define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
41 #define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
42 #define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
43 #define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
44 #define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
45 #define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
46 #define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
47 #define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
48 #define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
49 #define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
50 #define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
51 #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
52 #define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
53 #define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
54 #define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
55 #define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
56 #define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
57 #define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
58 #define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
59 #define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
60 #define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
61 #define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
62 #define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
63 #define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
64 #define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
65 #define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
66 #define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
67 #define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
68 #define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
69 #define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
70 #define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
71 #define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
72 #define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
73 #define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
74 #define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
75 #define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
76 #define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
77 #define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
78 #define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
79 #define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
80 #define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
81 #define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
82 #define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
83 #define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
84 #define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
85 #define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
86 #define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
87 #define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
88 #define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
89 #define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
90 #define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
91 #define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
92 #define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
93 #define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
94 #define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
95 #define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
96 #define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
97 #define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
98 #define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
99 #define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
100 #define USB_FADDR 0xFFC03800 /* Function address register */
101 #define USB_POWER 0xFFC03804 /* Power management register */
102 #define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
103 #define USB_INTRRX 0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */
104 #define USB_INTRTXE 0xFFC03810 /* Interrupt enable register for IntrTx */
105 #define USB_INTRRXE 0xFFC03814 /* Interrupt enable register for IntrRx */
106 #define USB_INTRUSB 0xFFC03818 /* Interrupt register for common USB interrupts */
107 #define USB_INTRUSBE 0xFFC0381C /* Interrupt enable register for IntrUSB */
108 #define USB_FRAME 0xFFC03820 /* USB frame number */
109 #define USB_INDEX 0xFFC03824 /* Index register for selecting the indexed endpoint registers */
110 #define USB_TESTMODE 0xFFC03828 /* Enabled USB 20 test modes */
111 #define USB_GLOBINTR 0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
112 #define USB_GLOBAL_CTL 0xFFC03830 /* Global Clock Control for the core */
113 #define USB_TX_MAX_PACKET 0xFFC03840 /* Maximum packet size for Host Tx endpoint */
114 #define USB_CSR0 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
115 #define USB_TXCSR 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
116 #define USB_RX_MAX_PACKET 0xFFC03848 /* Maximum packet size for Host Rx endpoint */
117 #define USB_RXCSR 0xFFC0384C /* Control Status register for Host Rx endpoint */
118 #define USB_COUNT0 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
119 #define USB_RXCOUNT 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
120 #define USB_TXTYPE 0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
121 #define USB_NAKLIMIT0 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
122 #define USB_TXINTERVAL 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
123 #define USB_RXTYPE 0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
124 #define USB_RXINTERVAL 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
125 #define USB_TXCOUNT 0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
126 #define USB_EP0_FIFO 0xFFC03880 /* Endpoint 0 FIFO */
127 #define USB_EP1_FIFO 0xFFC03888 /* Endpoint 1 FIFO */
128 #define USB_EP2_FIFO 0xFFC03890 /* Endpoint 2 FIFO */
129 #define USB_EP3_FIFO 0xFFC03898 /* Endpoint 3 FIFO */
130 #define USB_EP4_FIFO 0xFFC038A0 /* Endpoint 4 FIFO */
131 #define USB_EP5_FIFO 0xFFC038A8 /* Endpoint 5 FIFO */
132 #define USB_EP6_FIFO 0xFFC038B0 /* Endpoint 6 FIFO */
133 #define USB_EP7_FIFO 0xFFC038B8 /* Endpoint 7 FIFO */
134 #define USB_OTG_DEV_CTL 0xFFC03900 /* OTG Device Control Register */
135 #define USB_OTG_VBUS_IRQ 0xFFC03904 /* OTG VBUS Control Interrupts */
136 #define USB_OTG_VBUS_MASK 0xFFC03908 /* VBUS Control Interrupt Enable */
137 #define USB_LINKINFO 0xFFC03948 /* Enables programming of some PHY-side delays */
138 #define USB_VPLEN 0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */
139 #define USB_HS_EOF1 0xFFC03950 /* Time buffer for High-Speed transactions */
140 #define USB_FS_EOF1 0xFFC03954 /* Time buffer for Full-Speed transactions */
141 #define USB_LS_EOF1 0xFFC03958 /* Time buffer for Low-Speed transactions */
142 #define USB_APHY_CNTRL 0xFFC039E0 /* Register that increases visibility of Analog PHY */
143 #define USB_APHY_CALIB 0xFFC039E4 /* Register used to set some calibration values */
144 #define USB_APHY_CNTRL2 0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
145 #define USB_PHY_TEST 0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */
146 #define USB_PLLOSC_CTRL 0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */
147 #define USB_SRP_CLKDIV 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
148 #define USB_EP_NI0_TXMAXP 0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */
149 #define USB_EP_NI0_TXCSR 0xFFC03A04 /* Control Status register for endpoint 0 */
150 #define USB_EP_NI0_RXMAXP 0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */
151 #define USB_EP_NI0_RXCSR 0xFFC03A0C /* Control Status register for Host Rx endpoint0 */
152 #define USB_EP_NI0_RXCOUNT 0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */
153 #define USB_EP_NI0_TXTYPE 0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
154 #define USB_EP_NI0_TXINTERVAL 0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */
155 #define USB_EP_NI0_RXTYPE 0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
156 #define USB_EP_NI0_RXINTERVAL 0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
157 #define USB_EP_NI0_TXCOUNT 0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
158 #define USB_EP_NI1_TXMAXP 0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */
159 #define USB_EP_NI1_TXCSR 0xFFC03A44 /* Control Status register for endpoint1 */
160 #define USB_EP_NI1_RXMAXP 0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */
161 #define USB_EP_NI1_RXCSR 0xFFC03A4C /* Control Status register for Host Rx endpoint1 */
162 #define USB_EP_NI1_RXCOUNT 0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */
163 #define USB_EP_NI1_TXTYPE 0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
164 #define USB_EP_NI1_TXINTERVAL 0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */
165 #define USB_EP_NI1_RXTYPE 0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
166 #define USB_EP_NI1_RXINTERVAL 0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
167 #define USB_EP_NI1_TXCOUNT 0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
168 #define USB_EP_NI2_TXMAXP 0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */
169 #define USB_EP_NI2_TXCSR 0xFFC03A84 /* Control Status register for endpoint2 */
170 #define USB_EP_NI2_RXMAXP 0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */
171 #define USB_EP_NI2_RXCSR 0xFFC03A8C /* Control Status register for Host Rx endpoint2 */
172 #define USB_EP_NI2_RXCOUNT 0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */
173 #define USB_EP_NI2_TXTYPE 0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
174 #define USB_EP_NI2_TXINTERVAL 0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */
175 #define USB_EP_NI2_RXTYPE 0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
176 #define USB_EP_NI2_RXINTERVAL 0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
177 #define USB_EP_NI2_TXCOUNT 0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
178 #define USB_EP_NI3_TXMAXP 0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */
179 #define USB_EP_NI3_TXCSR 0xFFC03AC4 /* Control Status register for endpoint3 */
180 #define USB_EP_NI3_RXMAXP 0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */
181 #define USB_EP_NI3_RXCSR 0xFFC03ACC /* Control Status register for Host Rx endpoint3 */
182 #define USB_EP_NI3_RXCOUNT 0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */
183 #define USB_EP_NI3_TXTYPE 0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
184 #define USB_EP_NI3_TXINTERVAL 0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */
185 #define USB_EP_NI3_RXTYPE 0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
186 #define USB_EP_NI3_RXINTERVAL 0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
187 #define USB_EP_NI3_TXCOUNT 0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
188 #define USB_EP_NI4_TXMAXP 0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */
189 #define USB_EP_NI4_TXCSR 0xFFC03B04 /* Control Status register for endpoint4 */
190 #define USB_EP_NI4_RXMAXP 0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */
191 #define USB_EP_NI4_RXCSR 0xFFC03B0C /* Control Status register for Host Rx endpoint4 */
192 #define USB_EP_NI4_RXCOUNT 0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */
193 #define USB_EP_NI4_TXTYPE 0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
194 #define USB_EP_NI4_TXINTERVAL 0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */
195 #define USB_EP_NI4_RXTYPE 0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
196 #define USB_EP_NI4_RXINTERVAL 0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
197 #define USB_EP_NI4_TXCOUNT 0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
198 #define USB_EP_NI5_TXMAXP 0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */
199 #define USB_EP_NI5_TXCSR 0xFFC03B44 /* Control Status register for endpoint5 */
200 #define USB_EP_NI5_RXMAXP 0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */
201 #define USB_EP_NI5_RXCSR 0xFFC03B4C /* Control Status register for Host Rx endpoint5 */
202 #define USB_EP_NI5_RXCOUNT 0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */
203 #define USB_EP_NI5_TXTYPE 0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
204 #define USB_EP_NI5_TXINTERVAL 0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */
205 #define USB_EP_NI5_RXTYPE 0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
206 #define USB_EP_NI5_RXINTERVAL 0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
207 #define USB_EP_NI5_TXCOUNT 0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
208 #define USB_EP_NI6_TXMAXP 0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */
209 #define USB_EP_NI6_TXCSR 0xFFC03B84 /* Control Status register for endpoint6 */
210 #define USB_EP_NI6_RXMAXP 0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */
211 #define USB_EP_NI6_RXCSR 0xFFC03B8C /* Control Status register for Host Rx endpoint6 */
212 #define USB_EP_NI6_RXCOUNT 0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */
213 #define USB_EP_NI6_TXTYPE 0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
214 #define USB_EP_NI6_TXINTERVAL 0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */
215 #define USB_EP_NI6_RXTYPE 0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
216 #define USB_EP_NI6_RXINTERVAL 0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
217 #define USB_EP_NI6_TXCOUNT 0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
218 #define USB_EP_NI7_TXMAXP 0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */
219 #define USB_EP_NI7_TXCSR 0xFFC03BC4 /* Control Status register for endpoint7 */
220 #define USB_EP_NI7_RXMAXP 0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */
221 #define USB_EP_NI7_RXCSR 0xFFC03BCC /* Control Status register for Host Rx endpoint7 */
222 #define USB_EP_NI7_RXCOUNT 0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */
223 #define USB_EP_NI7_TXTYPE 0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
224 #define USB_EP_NI7_TXINTERVAL 0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */
225 #define USB_EP_NI7_RXTYPE 0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
226 #define USB_EP_NI7_RXINTERVAL 0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
227 #define USB_EP_NI7_TXCOUNT 0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
228 #define USB_DMA_INTERRUPT 0xFFC03C00 /* Indicates pending interrupts for the DMA channels */
229 #define USB_DMA0_CONTROL 0xFFC03C04 /* DMA master channel 0 configuration */
230 #define USB_DMA0_ADDRLOW 0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
231 #define USB_DMA0_ADDRHIGH 0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
232 #define USB_DMA0_COUNTLOW 0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
233 #define USB_DMA0_COUNTHIGH 0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
234 #define USB_DMA1_CONTROL 0xFFC03C24 /* DMA master channel 1 configuration */
235 #define USB_DMA1_ADDRLOW 0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
236 #define USB_DMA1_ADDRHIGH 0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
237 #define USB_DMA1_COUNTLOW 0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
238 #define USB_DMA1_COUNTHIGH 0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
239 #define USB_DMA2_CONTROL 0xFFC03C44 /* DMA master channel 2 configuration */
240 #define USB_DMA2_ADDRLOW 0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
241 #define USB_DMA2_ADDRHIGH 0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
242 #define USB_DMA2_COUNTLOW 0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
243 #define USB_DMA2_COUNTHIGH 0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
244 #define USB_DMA3_CONTROL 0xFFC03C64 /* DMA master channel 3 configuration */
245 #define USB_DMA3_ADDRLOW 0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
246 #define USB_DMA3_ADDRHIGH 0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
247 #define USB_DMA3_COUNTLOW 0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
248 #define USB_DMA3_COUNTHIGH 0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
249 #define USB_DMA4_CONTROL 0xFFC03C84 /* DMA master channel 4 configuration */
250 #define USB_DMA4_ADDRLOW 0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
251 #define USB_DMA4_ADDRHIGH 0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
252 #define USB_DMA4_COUNTLOW 0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
253 #define USB_DMA4_COUNTHIGH 0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
254 #define USB_DMA5_CONTROL 0xFFC03CA4 /* DMA master channel 5 configuration */
255 #define USB_DMA5_ADDRLOW 0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
256 #define USB_DMA5_ADDRHIGH 0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
257 #define USB_DMA5_COUNTLOW 0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
258 #define USB_DMA5_COUNTHIGH 0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
259 #define USB_DMA6_CONTROL 0xFFC03CC4 /* DMA master channel 6 configuration */
260 #define USB_DMA6_ADDRLOW 0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
261 #define USB_DMA6_ADDRHIGH 0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
262 #define USB_DMA6_COUNTLOW 0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
263 #define USB_DMA6_COUNTHIGH 0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
264 #define USB_DMA7_CONTROL 0xFFC03CE4 /* DMA master channel 7 configuration */
265 #define USB_DMA7_ADDRLOW 0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
266 #define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
267 #define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
268 #define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
270 #endif /* __BFIN_DEF_ADSP_BF526_proc__ */